MT48H4M16LFB4-10 TR Micron Technology Inc, MT48H4M16LFB4-10 TR Datasheet - Page 11

• Manufacturer Part Number: MT48H4M16LFB4-10 TR
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Temperature Compensated Self Refresh
allows the controller to program the refresh interval
during self refresh mode, according to the case tem-
perature of the mobile device. This allows great power
savings during SELF REFRESH during most operating
temperature ranges. Only during extreme tempera-
tures would the controller have to select the maximum
TCSR level. This would guarantee data during SELF
REFRESH.
the capacitor losing its charge over time. The refresh
rate is dependent on temperature. At higher tempera-
tures a capacitor loses charge quicker than at lower
temperatures, requiring the cells to be refreshed more
often. Historically, during self refresh, the refresh rate
has been set to accommodate the worst case, or high-
est temperature range expected.
sumed during refresh was unnecessarily high, because
the refresh rate was set to accommodate the higher
temperatures. Adjusting the refresh rate by setting E4
and E3 allows the SDRAM to accommodate more spe-
cific temperature regions during SELF REFRESH.
There are four temperature settings, which will vary
the SELF REFRESH current according to the selected
temperature. This selectable refresh rate will save
power when the SDRAM is operating at normal tem-
peratures.
Partial Array Self Refresh
the partial array self refresh (PASR) feature allows the
controller to select the amount of memory that will be
refreshed during SELF REFRESH. The refresh options
are all banks (banks 0, 1, 2, and 3); two banks (banks 0
and 1); and one bank (bank 0). Also included in the
refresh options are the 1/2 bank and 1/4 bank partial
array self refresh (bank 0). WRITE and READ com-
mands occur to any bank selected during standard
operation, but only the selected banks in PASR will be
refreshed during SELF REFRESH. It’s important to note
that data in unused banks, or portions of banks, will be
lost when PASR is used. Data will be lost in banks 1, 2,
and 3 when the one bank option is used.
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Temperature compensated self refresh (TCSR)
Every cell in the SDRAM requires refreshing due to
Thus, during ambient temperatures, the power con-
For further power savings during SELF REFRESH,
11
Driver Strength
used to select the driver strength of the DQ outputs.
This value should be set according to the application’s
requirements. Full drive strength was carried over
from standard SDRAM and is suitable to drive higher
load systems. Full drive strength is not recommended
for loads under 30pF. Half drive strength is intended
for multi-drop systems with various loads. This drive
option is not recommended for loads under 15pF.
Quarter drive strength is intended for lighter loads or
point-to-point systems.
NOTE:
1. E13 and E12 (BA1 and BA0) must be “1, 0” to select the
2. RFU: Reserved for future use
3. Default EMR values are full array for PASR, full drive
4. E11 = 0
5. E10, E11 = 0
E6
0
0
1
1 1
Bits E5 and E6 of the extended mode register can be
extended mode register (vs. the base mode register).
strength, and 85° for TCSR.
Figure 6: Extended Mode Register
E5
0
1
0
BA1
1
E13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Half Strength
Quarter Strength
Reserved
Driver Strength
Full Strength
E2
0
0
0
0
0
1
1
1
1
BA0
12
E12
All must be set to "0"
11
A11
E11
E1
10
0
0
1
1
0
0
1
1
A10
E10
3
9
A9
E9
E0
E4
8
A8
0
1
0
1
0
1
0
1
E8
1
0
0
1
A7 A6 A5 A4 A3
7
E7 E6 E5 E4 E3
E3
1
0
1
0
6
DS
Maximum Case Temp
Table
5
TCSR
4
MOBILE SDRAM
70˚C
45˚C
15˚C
85˚C
©2003 Micron Technology, Inc. All rights reserved.
3
Self Refresh Coverage
3
Two Banks (Bank 0,1)
A2 A1 A0
E2 E1 E0
2
PASR
One Bank (Bank 0)
1/2 Bank (Bank 0)
1/4 Bank (Bank 0)
Four Banks
1
64Mb: x16
RFU
RFU
RFU
0
3
Address Bus
Extended Mode
Register (Ex)
4
5