MT48H4M16LFB4-10 TR Micron Technology Inc, MT48H4M16LFB4-10 TR Datasheet - Page 26

• Manufacturer Part Number: MT48H4M16LFB4-10 TR
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 7:
Notes: 1-4: Notes appear below table
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
1. CKE
2. Current state is the state of the SDRAM immediately prior to clock edge n.
3. COMMAND
4. All states and sequences not shown are illegal or reserved.
5. Exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided
6. Exiting self refresh at clock edge n will put the device in the all banks idle state once
7. After exiting clock suspend at clock edge n, the device will resume operation and recognize the next command at clock
8. Deep power-down is a power-saving feature of this Mobile SDRAM device. This command is BURST TERMINATE when
CKE
that
NOP commands should be issued on any clock edges occurring during the
mands must be provided during
edge n + 1.
CKE is high and DEEP POWER DOWN when CKE is low.
H
H
L
L
n-1
n
t
CKS is met).
is the logic state of CKE at clock edge n; CKE
CKE
H
H
L
L
n
Truth Table 2 – CKE
n
is the command registered at clock edge n, and ACTION
Reading or Writing
Deep Power-Down
Deep Power-Down
CURRENT STATE
Clock Suspend
Clock Suspend
All Banks Idle
All Banks Idle
All Banks Idle
Power-Down
Power-Down
Self Refresh
Self Refresh
t
XSR period.
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
COMMAND INHIBIT or NOP
BURST TERMINATE
n-1
See Truth Table 3
AUTO REFRESH
COMMAND
was the state of CKE at the previous clock edge.
VALID
26
X
X
X
X
X
X
n
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n
is a result of COMMAND
t
XSR period. A minimum of two NOP com-
Maintain Deep Power-Down
Deep Power-Down Entry
Maintain Clock Suspend
Exit Deep Power-Down
Maintain Power-Down
Maintain Self Refresh
Clock Suspend Entry
Exit Clock Suspend
Power-Down Entry
Self Refresh Entry
t
Exit Power-Down
Exit Self Refresh
XSR is met. COMMAND INHIBIT or
ACTION
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
n
.
n
64Mb: x16
NOTES
8
5
8
6
7
8