MT48H4M16LFB4-10 TR Micron Technology Inc, MT48H4M16LFB4-10 TR Datasheet - Page 24

• Manufacturer Part Number: MT48H4M16LFB4-10 TR
• Description: IC SDRAM 64MBIT 100MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-10 TR

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 100MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Concurrent Auto Precharge
precharge, which allows an access command (READ or
WRITE) to another bank while an access command
with auto precharge enabled is executing. Four cases
where concurrent auto precharge occurs are defined
below.
READ with Auto Precharge
NOTE:
NOTE:
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Micron SDRAM devices support Concurrent Auto
precharge): A READ to bank m will interrupt a READ
on bank n, two or three clocks later, depending on
1. Interrupted by a READ (with or without auto
DQM is LOW.
DQM is HIGH at T2 to prevent D
Figure 28: READ With Auto Precharge Interrupted by a WRITE
Figure 27: READ With Auto Precharge Interrupted by a READ
Internal
States
Internal
States
COMMAND
ADDRESS
COMMAND
BANK m
BANK n
ADDRESS
BANK m
BANK n
CLK
DQ
DQM
CLK
DQ
1
Active
Page
Page Active
T0
NOP
READ - AP
BANK n,
BANK n
COL a
T0
OUT
READ with Burst of 4
READ - AP
BANK n,
Page Active
CAS Latency = 3 (BANK n)
-a+1 from contending with D
BANK n
COL a
T1
Page Active
T1
NOP
READ with Burst of 4
CAS Latency = 3 (BANK n)
T2
NOP
T2
NOP
24
BANK m,
READ - AP
T3
BANK m
COL d
T3
D
Interrupt Burst, Precharge
NOP
CAS Latency = 3 (BANK m)
OUT
READ with Burst of 4
a
CAS latency. The precharge to bank n will begin
when the READ to bank m is registered (Figure 27,
READ With Auto Precharge Interrupted by a READ).
precharge): When a WRITE to bank m registers, a
READ on bank n will be interrupted. DQM should
be used two clocks prior to the WRITE command to
prevent bus contention. The precharge to bank n
will begin when the WRITE to bank m is registered
(Figure 28, READ With Auto Precharge Interrupted
by a WRITE).
BANK m,
2. Interrupted by a WRITE (with or without auto
T4
WRITE - AP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
COL d
NOP
T4
BANK m
D
D
d
IN
Interrupt Burst, Precharge
OUT
a
t
WRITE with Burst of 4
RP - BANK n
T5
T5
NOP
d + 1
NOP
D
a + 1
D
IN
OUT
t
IN
RP - BANK n
-d at T4.
T6
T6
NOP
d + 2
NOP
D
DON’T CARE
D
IN
OUT
d
DON’T CARE
Idle
T7
NOP
T7
t WR - BANK m
t RP - BANK m
d + 3
NOP
D
Precharge
D
d + 1
IN
Write-Back
OUT
MOBILE SDRAM
Idle
©2003 Micron Technology, Inc. All rights reserved.
64Mb: x16