MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 19

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

BURST TERMINATE command, and fixed-length
READ bursts may be truncated with a BURST TERMI-
NATE command, provided that auto precharge was
not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at
which the last desired data element is valid, where x
equals the CAS latency minus one. This is shown in
Figure 15, Terminating a READ Burst, for each possible
CAS latency; data element n + 3 is the last desired data
element of a longer burst.
WRITEs
as shown in Figure 16, WRITE Command.
vided with the WRITE command, and auto precharge
is either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is pre-
charged at the completion of the burst. For the generic
WRITE commands used in the following illustrations,
auto precharge is disabled.
will be registered coincident with the WRITE com-
mand. Subsequent data elements will be registered on
each successive positive clock edge. Upon completion
of a fixed-length burst, assuming no other commands
have been initiated, the DQ will remain High-Z and
any additional input data will be ignored (see Figure
18, WRITE to WRITE). A full-page burst will continue
until terminated. (At the end of the page, it will wrap to
column 0 and continue.)
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Full-page READ bursts can be truncated with the
WRITE bursts are initiated with a WRITE command,
The starting column and bank addresses are pro-
During WRITE bursts, the first valid data-in element
19
subsequent WRITE command, and data for a fixed-
length WRITE burst may be immediately followed by
data for a WRITE command. The new WRITE com-
mand can be issued on any clock following the previ-
ous WRITE command, and the data provided
coincident with the new command applies to the new
command. An example is shown in Figure 19, Random
WRITE Cycles. Data n + 1 is either the last of a burst of
two or the last desired of a longer burst. The 64Mb
SDRAM uses a pipelined architecture and therefore
does not require the 2n rule associated with a prefetch
architecture. A WRITE command can be initiated on
any clock cycle following a previous WRITE command.
Full-speed random write accesses within a page can be
performed to the same bank, as shown in Figure 19, or
each subsequent WRITE may be performed to a differ-
ent bank.
Data for any WRITE burst may be truncated with a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Figure 16: WRITE Command
A9, A11
BA0, 1
A0-A8
RAS#
CAS#
WE#
CKE
A10
CLK
CS#
HIGH
VALID ADDRESS
DISABLE AUTO PRECHARGE
ENABLE AUTO PRECHARGE
MOBILE SDRAM
©2003 Micron Technology, Inc. All rights reserved.
ADDRESS
ADDRESS
COLUMN
BANK
64Mb: x16
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