MT48H4M16LFB4-8 IT Micron Technology Inc, MT48H4M16LFB4-8 IT Datasheet - Page 23

• Manufacturer Part Number: MT48H4M16LFB4-8 IT
• Description: IC SDRAM 64MBIT 125MHZ 54VFBGA
• Manufacturer: Micron Technology Inc

Specifications of MT48H4M16LFB4-8 IT

• Format - Memory: RAM
• Memory Type: Mobile SDRAM
• Memory Size: 64M (4M x 16)
• Speed: 125MHz
• Interface: Parallel
• Voltage - Supply: 1.7 V ~ 1.9 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 54-VFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

pins at the time of a suspended internal clock edge is
ignored; any data present on the DQ pins remains
driven; and burst counters are not incremented, as
long as the clock is suspended. (See examples in Figure
25, Clock Suspend During WRITE Burst, and Figure 26,
Clock Suspend During READ Burst.)
HIGH; the internal clock and related operation will
resume on the subsequent positive clock edge.
BURST READ/SINGLE WRITE
gramming the write burst mode bit (M9) in the mode
register to a logic 1. In this mode, all WRITE com-
mands result in the access of a single column location
(burst of one), regardless of the programmed burst
pdf: 09005aef80a63953, source: 09005aef808a7edc
Y25L_64Mb_2.fm - Rev. E 11/04 EN
Clock suspend mode is exited by registering CKE
The burst read/single write mode is entered by pro-
23
length. READ commands access columns according to
the programmed burst length and sequence, just as in
the normal mode of operation (M9 = 0).
Figure 25: Clock Suspend During WRITE
NOTE:
NOTE:
Figure 26: Clock Suspend During READ
COMMAND
INTERNAL
ADDRESS
COMMAND
INTERNAL
CLOCK
ADDRESS
CLK
CKE
CLOCK
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DQ
CKE
CLK
D
IN
For this example, burst length = 4 or greater,
and DM is LOW.
For this example, CAS latency = 2, burst
length = 4 or greater, and DQM is LOW.
T0
BANK,
COL n
READ
NOP
T0
T1
NOP
WRITE
BANK,
COL n
D
T1
n
IN
T2
NOP
Burst
Burst
D
OUT
n
T2
MOBILE SDRAM
T3
©2003 Micron Technology, Inc. All rights reserved.
T3
n + 1
D
OUT
T4
NOP
64Mb: x16
NOP
n + 1
T4
D
IN
T5
NOP
n + 2
D
DON’T CARE
OUT
DON’T CARE
T5
NOP
n + 2
D
IN
T6
NOP
D
n + 3
OUT