M25P128-VME6TG NUMONYX, M25P128-VME6TG Datasheet - Page 14

• Manufacturer Part Number: M25P128-VME6TG
• Description: IC FLASH 128MBIT 50MHZ 8VDFPN
• Manufacturer: NUMONYX
• Series: Forté™r

Specifications of M25P128-VME6TG

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 128M (16M x 8)
• Speed: 50MHz
• Interface: SPI, 3-Wire Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-VDFPN
• Cell Type: NOR
• Density: 128Mb
• Access Time (max): 8ns
• Interface Type: Serial (SPI)
• Boot Type: Not Required
• Address Bus: 1b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: VDFPN EP
• Sync/async: Synchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 16M
• Supply Current: 8mA
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: M25P128-VME6TGCT

4.8
14/47
Table 2.
1.
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in
During the Hold condition, the Serial Data Output (Q) is high impedance, and Serial Data
Input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
BP2 Bit BP1 Bit BP0 Bit
Status Register content
The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are 0.
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Protected area sizes
0
1
0
1
0
1
0
1
Figure
none
Upper 64th (1 Sector, 2Mb)
Upper 32nd (2 Sectors, 4Mb)
Upper 16nd (4 Sectors, 8Mb)
Upper 8nd (8 Sectors, 16Mb)
Upper Quarter (16 Sectors, 32Mb) Lower 3 Quarters (Sectors 0 to 47)
Upper Half (32 Sectors, 64Mb)
All sectors (64 Sectors, 128Mb)
6).
Protected area
Memory content
Figure
All Sectors (Sectors 0 to 63)
Sectors 0 to 62
Sectors 0 to 61
Sectors 0 to 59
Sectors 0 to 55
Lower Half (Sectors 0 to 31)
none
6).
Unprotected area
(1)