PCA9626B,118 NXP Semiconductors, PCA9626B,118 Datasheet
PCA9626B,118
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PCA9626B,118 Summary of contents
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PCA9626 24-bit Fm+ I Rev. 02 — 31 August 2009 1. General description The PCA9626 dimming and blinking 100 mA Red/Green/Blue/Amber (RGBA) LEDs. Each LED output has its own 8-bit resolution (256 steps) fixed frequency individual PWM ...
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... NXP Semiconductors 2. Features I 24 LED drivers. Each output programmable at: N Off Programmable LED brightness N Programmable group dimming/blinking mixed with individual LED brightness I 1 MHz Fast-mode Plus compatible I on SDA output for driving high capacitive buses I 256-step (8-bit) linear programmable brightness per LED output varying from fully off ...
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... NXP Semiconductors 3. Applications I RGB or RGBA LED drivers I LED status information I LED displays I LCD backlights I Keypad backlights for cellular phones or handheld devices 4. Ordering information Table 1. Ordering information Type number Topside mark PCA9626B PCA9626 PCA9626BS PCA9626 PCA9626_2 Product data sheet Package Name Description LQFP48 plastic low profi ...
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PCA9626 SCL INPUT FILTER SDA POWER- RESET V SS PWM REGISTER X BRIGHTNESS CONTROL 24.3 kHz 97 kHz 25 MHz OSCILLATOR OE Remark: Only one LED output shown for clarity. Fig 1. Block diagram of PCA9626 A0 A1 ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Fig 3. PCA9626_2 Product data sheet LED0 2 3 LED1 LED2 4 LED3 PCA9626B LED4 8 LED5 9 10 LED6 LED7 Pin configuration for LQFP48 terminal 1 index area LED0 2 3 LED1 LED2 4 LED3 LED4 8 LED5 9 10 LED6 LED7 ...
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... NXP Semiconductors 6.2 Pin description Table 2. Symbol LED22 LED23 LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7 LED8 LED9 LED10 LED11 LED12 LED13 LED14 LED15 LED16 LED17 LED18 LED19 SCL SDA V DD LED20 LED21 PCA9626_2 Product data sheet Pin description Pin ...
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... NXP Semiconductors [1] HVQFN48 package supply ground is connected to both V be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the PCB in the thermal pad region ...
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... NXP Semiconductors The last bit of the address byte defines the operation to be performed. When set to logic 1 a read is selected, while a logic 0 selects a write operation. 7.1.2 LED All Call I • Default power-up value (ALLCALLADR register): E0h or 1110 000 • Programmable through I • ...
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... NXP Semiconductors 7.2 Control register Following the successful acknowledgement of the slave address, LED All Call address or LED Sub Call address, the bus master will send a byte to the PCA9626, which will be stored in the Control register. The lowest 6 bits are used as a pointer to determine which register will be accessed (D[5:0]) ...
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... NXP Semiconductors AIF + AI[1:0] = 101b is used when the 16 LED drivers must be individually programmed with different values during the same I setting to another color setting. AIF + AI[1:0] = 110b is used when the LED drivers must be globally programmed with different settings during the same I or blinking change. ...
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... NXP Semiconductors [1][2] Table 4. Register summary Register number D5 D4 (hex [1] Only D[5: 0000 to 10 0110 are allowed and will be acknowledged. D[5: 0111 to 11 1111 are reserved and may not be acknowledged. [2] When writing to the Control register, bit 6 should be programmed with logic 0 for proper device operation. ...
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... NXP Semiconductors 7.3.1 Mode register 1, MODE1 Table 5. MODE1 - Mode register 1 (address 00h) bit description Legend: * default value. Bit Symbol Access 7 AI2 read only 6 AI1 R/W 5 AI0 R/W 4 SLEEP R/W 3 SUB1 R/W 2 SUB2 R/W 1 SUB3 R/W 0 ALLCALL R/W [1] It takes 500 s max. for the oscillator and running once SLEEP bit has been set to logic 1. Timings on LEDn outputs are not guaranteed if PWMx, GRPPWM or GRPFREQ registers are accessed within the 500 s window ...
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... NXP Semiconductors 7.3.3 PWM0 to PWM23, individual brightness control Table 7. Legend: * default value. Address 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h A 97 kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0 % duty cycle = LED output off) to FFh (99 ...
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... NXP Semiconductors 7.3.4 GRPPWM, group duty cycle control Table 8. Legend: * default value Address 1Ah When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed frequency signal is superimposed with the 97 kHz individual brightness control signal. GRPPWM is then used as a global brightness control allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a ‘ ...
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... NXP Semiconductors 7.3.6 CHASE control Table 10. Legend: * default value. Address 1Ch CHASE is used to program the LED output ON/OFF pattern. The contents of the CHASE register is used to enable one of the LED output patterns, as indicated in By repeated, sequential access to this table via the CHASE register, a chase pattern, e.g., marquee effect, can be easily programmed with minimal number of commands ...
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Table 11. CHASE sequence X = enabled; empty cell = disabled. Command Hex LED channel ...
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Table 11. CHASE sequence …continued X = enabled; empty cell = disabled. Command Hex LED channel ...
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Table 11. CHASE sequence …continued X = enabled; empty cell = disabled. Command Hex LED channel ...
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Table 11. CHASE sequence …continued X = enabled; empty cell = disabled. Command Hex LED channel ...
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Table 11. CHASE sequence …continued X = enabled; empty cell = disabled. Command Hex LED channel ...
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Table 11. CHASE sequence …continued X = enabled; empty cell = disabled. Command Hex LED channel ...
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... NXP Semiconductors 7.3.7 LEDOUT0 to LEDOUT5, LED driver output state Table 12. Legend: * default value. Address 1Dh 1Eh 1Fh 20h 21h 22h LDRx = 00 — LED driver x is off (default power-up state). LDRx = 01 — LED driver x is fully on (individual brightness and group dimming/blinking not controlled). ...
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... NXP Semiconductors 7.3.8 SUBADR1 to SUBADR3, I Table 13. Legend: * default value. Address 23h 24h 25h Subaddresses are programmable through the I E4h, E8h, and the device(s) will not acknowledge these addresses right after power-up (the corresponding SUBx bit in MODE1 register is equal to 0). Once subaddresses have been programmed to their right values, SUBx bits need to be set to logic 1 in order to have the device acknowledging these addresses (MODE1 register) ...
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... NXP Semiconductors 7.4 Active LOW output enable input The active LOW output enable (OE) pin, allows to enable or disable all the LED outputs at the same time. • When a LOW level is applied to OE pin, all the LED outputs are enabled as defined by the CHASE register. ...
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... NXP Semiconductors b. Byte 2 = 5Ah: the PCA9626 acknowledges this value only. If byte 2 is not equal to 5Ah, then the PCA9626 does not acknowledge it. If more than 2 bytes of data are sent, the PCA9626 does not acknowledge any more. 5. Once the right 2 bytes (SWRST data byte 1 and byte 2 only) have been sent and ...
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... NXP Semiconductors 8. Characteristics of the I 2 The I C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device ...
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... NXP Semiconductors SDA SCL MASTER TRANSMITTER/ RECEIVER Fig 10. System configuration 8.3 Acknowledge The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse ...
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... NXP Semiconductors 9. Bus transactions slave address START condition (1) See Table 4 for register definition. Fig 12. Write to a specific register slave address START condition R/W acknowledge from slave SUBADR3 register (cont.) A acknowledge from slave Fig 13. Write to all registers using the Auto-Increment feature ...
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START condition R/W register selection acknowledge from slave Auto-Increment on PWM22 register data PWM23 register data (cont.) A acknowledge from slave This example ...
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... NXP Semiconductors slave address START condition R/W acknowledge from slave data from MODE2 register (cont.) A acknowledge from master data from last read byte (cont not acknowledge STOP from master condition This example assumes that the MODE1[ and MODE1[ Fig 15. Read all registers using the Auto-Increment feature ...
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... NXP Semiconductors 10. Application design-in information V = 2 C-BUS/SMBus MASTER SDA SCL OE (1) OE requires pull-up resistor if control signal from the master is open-drain C-bus address = 0010 101x. Remark: During power-down, slow decay of voltage supplies may keep LEDs illuminated. Consider disabling LED outputs using HIGH level applied to OE pin. ...
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... NXP Semiconductors 10.1 Junction temperature calculation A device junction temperature can be calculated when the ambient temperature or the case temperature is known. When the ambient temperature is known, the junction temperature is calculated using Equation 4 power dissipation amb where junction temperature j T amb R th(j- (device) total power dissipation ...
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... NXP Semiconductors 10.1.1 Example th(j-a) T amb LED output low voltage (LED V LED output current per channel = 80 mA Number of outputs = 24 I DD(max) V DD(max C-bus clock (SCL) maximum sink current = C-bus data (SDA) maximum sink current = Find P – output total power = 30 mA – chip core power consumption = 18 mA – ...
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... NXP Semiconductors 1. Find P – output current (60 mA – output current (50 mA – output current (40 mA – output current (20 mA – output current (1 mA Output total power = 341.5 mW – chip core power consumption = 18 mA – SCL power dissipation = 25 mA – SDA power dissipation = 25 mA ...
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... NXP Semiconductors Table 16. Measurement amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb maximum power dissipation (chip + output drivers) maximum power dissipation (output drivers only) maximum drive current per channel amb ...
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... NXP Semiconductors 13. Static characteristics Table 18. Static characteristics Symbol Parameter Supply V supply voltage DD I supply current DD I standby current stb V power-on reset voltage POR Input SCL; input/output SDA V LOW-level input voltage IL V HIGH-level input voltage IH I LOW-level output current OL I leakage current ...
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... NXP Semiconductors [2] Each bit must be limited to a maximum of 100 mA and the total package limited to 2400 mA due to internal busing limits. 14. Dynamic characteristics Table 19. Dynamic characteristics Symbol Parameter f SCL clock frequency SCL t bus free time BUF between a STOP and START condition t hold time (repeated) HD ...
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... NXP Semiconductors Table 19. Dynamic characteristics Symbol Parameter Output port timing t delay time from SCL d(SCL-Q) to data output t delay time from SDA d(SDA-Q) to data output [ time for Acknowledgement signal from SCL LOW to SDA (out) LOW. VD;ACK [ minimum time for SDA data out to be valid following SCL LOW. ...
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... NXP Semiconductors START protocol condition (S) t SU;STA SCL t BUF SDA t HD;STA Rise and fall times refer Fig 19. I C-bus timing diagram 15. Test information Fig 20. Test circuitry for switching times PCA9626_2 Product data sheet bit 7 bit 6 MSB (A6) (A7 LOW HIGH SCL SU;DAT HD ...
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... NXP Semiconductors 16. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors HVQFN48: plastic thermal enhanced very thin quad flat package; no leads; 48 terminals; body 0.85 mm terminal 1 index area terminal 1 48 index area DIMENSIONS (mm are the original dimensions) (1) A UNIT max 0.05 0. 0.2 0.00 0.15 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included ...
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... NXP Semiconductors 17. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards. 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 18.4 Reflow soldering Key characteristics in reflow soldering are: • ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 19. Abbreviations Table 22. Acronym ACK CDM DUT ESD FET HBM 2 I C-bus LED LSB MM MSB ...
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... NXP Semiconductors 20. Revision history Table 23. Revision history Document ID Release date PCA9626_2 20090831 • Modifications: Table 11 “CHASE sequence” commands) • Section 7.4 “Active LOW output enable • Figure 17 “Typical • Added (new) • Section 11 “Limiting – Table 15 “Limiting – Added (new) capability” ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 7 7.1 Device addresses . . . . . . . . . . . . . . . . . . . . . . . 7 2 7.1.1 Regular I C-bus slave address . . . . . . . . . . . . . 7 2 7.1.2 LED All Call I C-bus address . . . . . . . . . . . . . . ...