PCA9626B,118 NXP Semiconductors, PCA9626B,118 Datasheet - Page 14

IC LED DRIVER RGBA 48-LQFP

PCA9626B,118

Manufacturer Part Number
PCA9626B,118
Description
IC LED DRIVER RGBA 48-LQFP
Manufacturer
NXP Semiconductors
Type
RGBA LED Driverr
Datasheets

Specifications of PCA9626B,118

Package / Case
48-LQFP
Topology
Open Drain, PWM
Number Of Outputs
24
Internal Driver
Yes
Type - Primary
Backlight, LED Blinker
Type - Secondary
RGBA
Frequency
1MHz
Voltage - Supply
2.3 V ~ 5.5 V
Voltage - Output
40V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 85°C
Current - Output / Channel
100mA
Internal Switch(s)
Yes
Number Of Segments
24
Low Level Output Current
100000 uA (Min)
Operating Supply Voltage
2.3 V to 5.5 V
Maximum Supply Current
18000 uA
Maximum Power Dissipation
1800 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Efficiency
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4774-2

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PCA9626B,118
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Part Number:
PCA9626B,118
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
PCA9626_2
Product data sheet
7.3.4 GRPPWM, group duty cycle control
7.3.5 GRPFREQ, group frequency
Table 8.
Legend: * default value
When DMBLNK bit (MODE2 register) is programmed with logic 0, a 190 Hz fixed
frequency signal is superimposed with the 97 kHz individual brightness control signal.
GRPPWM is then used as a global brightness control allowing the LED outputs to be
dimmed with the same value. The value in GRPFREQ is then a ‘Don’t care’.
General brightness for the 16 outputs is controlled through 256 linear steps from 00h
(0 % duty cycle = LED output off) to FFh (99.6 % duty cycle = maximum brightness).
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
When DMBLNK bit is programmed with logic 1, GRPPWM and GRPFREQ registers
define a global blinking pattern, where GRPFREQ contains the blinking period (from
24 Hz to 10.73 s) and GRPPWM the duty cycle (ON/OFF ratio in %).
Table 9.
Legend: * default value.
GRPFREQ is used to program the global blinking period when DMBLNK bit (MODE2
register) is equal to 1. Value in this register is a ‘Don’t care’ when DMBLNK = 0.
Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 to LEDOUT5
registers).
Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz)
to FFh (10.73 s).
duty cycle
global blinking period
Address
1Ah
Address
1Bh
GRPPWM - Group brightness control register (address 1Ah) bit description
Register
GRPPWM
GRPFREQ - Group Frequency register (address 1Bh) bit description
Register
GRPFREQ
=
GDC 7:0
-------------------------- -
256
Rev. 02 — 31 August 2009
Bit
7:0
Bit
7:0
=
GFRQ 7:0
--------------------------------------- - s
Symbol
GDC[7:0]
Symbol
GFRQ[7:0]
24
+
1
Access Value
R/W
Access Value
R/W
24-bit Fm+ I
1111 1111
0000 0000* GRPFREQ register
2
C-bus 100 mA 40 V LED driver
Description
GRPPWM register
Description
PCA9626
© NXP B.V. 2009. All rights reserved.
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