ISL62870HRUZ-T Intersil, ISL62870HRUZ-T Datasheet - Page 11

• Manufacturer Part Number: ISL62870HRUZ-T
• Description: IC CTRLR VREG PWM DC/DC 16-TQFN
• Manufacturer: Intersil

Specifications of ISL62870HRUZ-T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-UTQFN (16-µTQFN)
• Frequency-max: 330kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts.
Selecting the LC Output Filter
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
shown in Equation 13:
The output inductor peak-to-peak ripple current is written as
shown in Equation 14:
A typical step-down DC/DC converter will have an I
20% to 40% of the maximum DC output load current. The
value of I
MOSFET switching loss, inductor core loss, and the resistive
loss of the inductor winding. The DC copper loss of the
inductor can be estimated using Equation 15:
Where I
The copper loss can be significant so attention has to be given
to the DCR selection. Another factor to consider when choosing
the inductor is its saturation characteristics at elevated
temperature. A saturated inductor could cause destruction of
circuit components, as well as nuisance OCP faults.
A DC/DC buck regulator must have output capacitance C
into which ripple current I
corresponding ripple voltage V
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
the capacitor. These two voltages are written as Equations 16
and 17:
and:
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V
inductance of the capacitor can cause a brief voltage dip if the
load transient has an extremely high slew rate. Low inductance
capacitors should be considered. A capacitor dissipates heat as
a function of RMS current and frequency. Be sure that I
shared by a sufficient quantity of paralleled capacitors so that
they operate below the maximum rated RMS current at F
Take into account that the rated value of a capacitor can fade
as much as 50% as the DC voltage across it increases.
I
D
P
ΔV
ΔV
P P
COPPER
–
=
ESR
C
---------
V
V
=
=
IN
O
-------------------------------- -
8 C
LOAD
=
V
------------------------------ -
P-P
O
⋅
F
I
P P
=
SW
I
⋅
P P
O
(
–
is selected based upon several criteria, such as
I
1 D
–
LOAD
⋅
is the converter output DC current.
⋅
–
F
⋅ SR
L
SW
E
)
2
⋅
DCR
P-P
can flow. Current I
11
P-P
across C
P-P
O,
is achieved. The
which is the
P-P
develops a
P-P
(EQ. 13)
(EQ. 15)
(EQ. 16)
(EQ. 17)
P-P
(EQ. 14)
SW
of
O
is
.
ISL62870
Selection of the Input Capacitor
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25 times greater
than the maximum input voltage, while a voltage rating of 1.5
times is a preferred rating. Figure 9 is a graph of the input
RMS ripple current, normalized relative to output load current,
as a function of duty cycle that is adjusted for converter
efficiency. The ripple current calculation is written as
expressed in Equation 18:
Where:
Duty cycle is written as expressed in Equation 19:
In addition to the bulk capacitance, some low ESL ceramic
capacitance is recommended to decouple between the drain
of the high-side MOSFET and the source of the low-side
MOSFET.
Selecting The Bootstrap Capacitor
Adding an external capacitor across the BOOT and PHASE
pins completes the bootstrap circuit. We selected the
bootstrap capacitor breakdown voltage to be at least 10V.
Although the theoretical maximum voltage of the capacitor is
PVCC - V
excursions below ground by the PHASE node requires that
I
D
IN_RMS
FIGURE 9. NORMALIZED RMS INPUT CURRENT FOR x = 0.8
- I
- x is a multiplier (0 to 1) corresponding to the inductor
- D is the duty cycle that is adjusted to take into account
=
peak-to-peak ripple amplitude expressed as a
percentage of I
the efficiency of the converter
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
MAX
------------------------- -
V
IN
0
0
V
⋅
=
DIODE
O
is the maximum continuous I
EFF
---------------------------------------------------------------------------------------------------- -
0.1
(
I
MAX
(voltage drop across the boot diode), large
0.2
2
MAX
⋅
(
D D
0.3
–
(0% to 100%)
I
0.4
2
MAX
DUTY CYCLE
)
)
x = 0.75
x = 0.25
x = 0.50
+
0.5
⎛
⎝
x = 1
x = 0
x I
⋅
MAX
0.6
LOAD
2
0.7
⋅
----- -
12
D
of the converter
⎞
⎠
0.8
August 14, 2008
0.9
(EQ. 18)
(EQ. 19)
FN6708.0
1.0