ISL62870HRUZ-T Intersil, ISL62870HRUZ-T Datasheet - Page 12

• Manufacturer Part Number: ISL62870HRUZ-T
• Description: IC CTRLR VREG PWM DC/DC 16-TQFN
• Manufacturer: Intersil

Specifications of ISL62870HRUZ-T

• Pwm Type: Controller
• Number Of Outputs: 1
• Frequency - Max: 330kHz
• Duty Cycle: 100%
• Voltage - Supply: 3.3 V ~ 25 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -10°C ~ 100°C
• Package / Case: 16-UTQFN (16-µTQFN)
• Frequency-max: 330kHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

we select a capacitor with at least a breakdown rating of 10V.
The bootstrap capacitor can be chosen from Equation 20:
Where:
As an example, suppose an upper MOSFET has a gate
charge, Q
the drive voltage over a PWM cycle is 200mV. One will find
that a bootstrap capacitance of at least 0.125µF is required.
The next larger standard value capacitance is 0.15µF. A
good quality ceramic capacitor such as X7R or X5R is
recommended.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function
of the switching frequency and total gate charge of the
selected MOSFETs. Calculating the power dissipation in the
driver for a desired application is critical to ensuring safe
operation. Exceeding the maximum allowable power
dissipation level will push the IC beyond the maximum
recommended operating junction temperature of +125°C.
When designing the application, it is recommended that the
following calculation be performed to ensure safe operation
at the desired frequency for the selected MOSFETs. The
power dissipated by the drivers is approximated using
Equation 21:
Where:
P
C
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
- Q
- ΔV
- F
- V
- V
=
BOOT
charge the gate of the upper MOSFET
capacitor
F
sw
sw
U
L
GATE
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
BOOT
is the lower gate driver bias supply voltage
is the upper gate driver bias supply voltage
(
≥
0.0
is the switching frequency of the PWM signal
1.5V
GATE
----------------------- -
ΔV
20nC
Q
is the amount of gate charge required to fully
GATE
BOOT
U
is the maximum decay across the BOOT
0.1
VOLTAGE
Q
, of 25nC at 5V and also assume the droop in
U
0.2
+
Q
GATE
V
L
Q
0.3
L
= 100nC
)
ΔV
+
0.4
P
12
BOOT_CAP
L
+
0.5
P
U
0.6
(V)
0.7
0.8
0.9
(EQ. 20)
(EQ. 21)
1.0
ISL62870
MOSFET Selection and Considerations
Typically, a MOSFET cannot tolerate even brief excursions
beyond their maximum drain to source voltage rating. The
MOSFETs used in the power stage of the converter should
have a maximum V
upper voltage tolerance of the input power source and the
voltage spike that occurs when the MOSFET switches off.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low switch charge so that
the device spends the least amount of time dissipating
power in the linear region. Unlike the low-side MOSFET,
which has the drain-source voltage clamped by its body
diode during turn-off, the high-side MOSFET turns off with
V
MOSFET emphasizes low r
minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be
assumed to be conductive only and is written as Equation 22:
For the high-side MOSFET, (HS), its conduction loss is
written as Equation 23:
For the high-side MOSFET, its switching loss is written as
Equation 24:
P
P
P
IN
CON_LS
CON_HS
SW_HS
- Q
- Q
- P
- P
1000
- V
the gate of the MOSFET and discrete capacitors
the gate of the MOSFET and discrete capacitors
900
800
700
600
500
400
300
200
100
L
U
FIGURE 11. POWER DISSIPATION vs FREQUENCY
U
L
OUT
0
is the quiescent power consumption of the lower driver
is the charge to be delivered by the lower driver into
is the quiescent power consumption of the upper driver
0
is the charge to be delivered by the upper driver into
=
≈
, plus the spike, across it. The preferred low-side
=
I
Q
Q
V
--------------------------------------------------------------------- -
200
LOAD
I
U
L
IN
LOAD
=200nC
=100nC
⋅
I
400
VALLEY
2
2
r ⋅
DS
r ⋅
DS ON
600
DS ON
rating that exceeds the sum of the
2
(
Q
(
Q
⋅
FREQUENCY (kHz)
L
t
U
=100nC
ON
800 1000 1200 1400 1600 1800 2000
)_LS
=50nC
DS(ON)
)_HS
⋅
F
⋅
SW
(
⋅
1 D
D
–
when fully saturated to
+
V
----------------------------------------------------------------- -
)
IN
⋅
I
PEAK
Q
Q
2
U
L
Q
Q
⋅
August 14, 2008
=50nC
t
=50nC
U
L
OFF
=50nC
=20nC
(EQ. 22)
(EQ. 23)
(EQ. 24)
FN6708.0
⋅
F
SW