ISL8103IRZ Intersil, ISL8103IRZ Datasheet - Page 15

• Manufacturer Part Number: ISL8103IRZ
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL8103IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12.6 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Gate Drive Voltage Versatility
The ISL8103 provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
ties the upper and lower drive rails together. Simply applying
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Initialization
Prior to initialization, proper conditions must exist on the
ENLL, VCC, PVCC and the REF0 and REF1 pins. When the
conditions are met, the controller begins soft-start. Once the
output voltage is within the proper window of operation, the
controller asserts PGOOD.
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL8103 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
FIGURE 10. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL8103 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL8103 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 5).
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
0.0
20nC
0.1
VOLTAGE
0.2
50nC
Q
GATE
0.3
= 100nC
ΔV
0.4
15
BOOT_CAP
0.5
0.6
(V)
0.7
0.8
0.9
1.0
ISL8103
When each of these conditions is true, the controller
immediately begins the soft-start sequence.
Soft-Start
During soft-start, the DAC voltage ramps linearly from zero
to the programmed level. The PWM signals remain in the
high-impedance state until the controller detects that the
ramping DAC level has reached the output-voltage level.
This protects the system against the large, negative inductor
currents that would otherwise occur when starting with a
pre-existing charge on the output as the controller attempted
to regulate to zero volts at the beginning of the soft-start
cycle. The Output soft-start time, t
period equal to 64 switching cycles after the ENLL has
exceeded its POR level, followed by a linear ramp with a rate
determined by the switching period, 1/F
2. The voltage on ENLL must be above 0.66V. The EN input
3. The driver bias voltage applied at the PVCC pins must
FIGURE 11. POWER SEQUENCING USING THRESHOLD-
allows for power sequencing between the controller bias
voltage and another voltage rail. The enable comparator
holds the ISL8103 in shutdown until the voltage at ENLL
rises above 0.66V. The enable comparator has 100mV of
hysteresis to prevent bounce.
reach the internal power-on reset (POR) rising threshold.
In order for the ISL8103 to begin operation, PVCC1 is the
only pin that is required to have a voltage applied that
exceeds POR. However, for 2 or 3-phase operation
PVCC2 and PVCC3 must also exceed the POR
threshold. Hysteresis between the rising and falling
thresholds assure that once enabled, the ISL8103 will not
inadvertently turn off unless the PVCC bias voltage drops
substantially (see “Electrical Specifications” on page 5).
CIRCUIT
FAULT LOGIC
SOFT-START
POR
AND
ISL8103 INTERNAL CIRCUIT
SENSITIVE ENABLE (ENLL) FUNCTION
ENABLE
COMPARATOR
+
-
0.66V
SS
, begins with a delay
VCC
ENLL
EXTERNAL CIRCUIT
PVCC1
sw
.
10.7kΩ
1.40kΩ
+12V
July 21, 2008
FN9246.1