ISL8103IRZ Intersil, ISL8103IRZ Datasheet - Page 24

• Manufacturer Part Number: ISL8103IRZ
• Description: IC CTRLR PWM BUCK 3PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL8103IRZ

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 1.5MHz
• Duty Cycle: 66.6%
• Voltage - Supply: 4.75 V ~ 12.6 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-VFQFN, 40-VFQFPN
• Frequency-max: 1.5MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

response, the output voltage initially deviates by an amount
as shown in Equation 36.
The filter capacitor must have sufficiently low ESL and ESR
so that ΔV < ΔV
Most capacitor solutions rely on a mixture of high frequency
capacitors with relatively low capacitance in combination
with bulk capacitors having high capacitance but limited
high-frequency performance. Minimizing the ESL of the
high-frequency capacitors allows them to support the output
voltage as the current increases. Minimizing the ESR of the
bulk capacitors allows them to supply the increased current
with less output voltage deviation.
The ESR of the bulk capacitors also creates the majority of
the output-voltage ripple. As the bulk capacitors sink and
source the inductor ac ripple current (see “Interleaving” on
page 9” and Equation 2), a voltage develops across the bulk
capacitor ESR equal to I
capacitors are selected, the maximum allowable ripple
voltage, V
inductance as shown in Equation 37.
Since the capacitors are supplying a decreasing portion of
the load current while the regulator recovers from the
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
ΔV
Equation 38 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 39
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
ΔV
L
L
≤
≥
MAX
≈
2 N C V
---------------------------------
(
ESR
(
⋅
ESL
(
. This places an upper limit on inductance.
ΔI
⋅
)
)
PP(MAX)
)
⋅
2
⋅
⋅
⎛
⎝
------------------------------------------------------------------- -
F
di
---- -
dt
V
SW
O
IN
+
⋅
MAX
(
–
⋅
ESR
ΔV
V
N V
, determines the lower limit on the
IN
.
MAX
⋅
⋅
) ΔI
V
OUT
⋅
(
C,P-P
P P
–
–
(
⎞ V
⎠
ΔI ESR
⋅
24
) MAX
(
⋅
(ESR). Thus, once the output
OUT
)
)
(EQ. 38)
(EQ. 36)
(EQ. 37)
ISL8103
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 18, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response
and small output-voltage ripple as outlined in “Output Filter
Design” on page 23. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R
are provided to assist in selecting the correct value for R
R
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs which is related to duty cycle and the number of
active phases.
L
FS
≤
(
--------------------------------- -
1.25
=
100
200
50
20
10
(
10
ΔI
FIGURE 23. R
) N C
[
⋅
)
10.61 1.035
2
100k
⋅
–
⋅
ΔV
MAX
SWITCHING FREQUENCY (Hz)
⋅
200k
log
FS
(
vs SWITCHING FREQUENCY
–
F
SW
(
ΔI ESR
FS
)
⋅
]
. Figure 23 and Equation 40
500k
)
⋅
⎛
⎝
V
IN
1M
–
V
O
⎞
⎠
July 21, 2008
2M
(EQ. 39)
(EQ. 40)
FN9246.1
FS
..