ISL6264CRZ Intersil, ISL6264CRZ Datasheet - Page 14

• Manufacturer Part Number: ISL6264CRZ
• Description: IC CORE CTRLR TWO-PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6264CRZ

• Applications: Controller, AMD Mobile Turion™
• Voltage - Input: 5 ~ 24 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
The ISL6264 is a two-phase regulator providing the power to
AMD Mobile CPUs such as the Turion processor and
includes integrated gate drivers for reduced system cost and
board area. The regulator provides optimum steady-state
and transient performance for microprocessor core
applications up to 50A. System efficiency is enhanced by
idling a phase at low-current and implementing automatic
DCM-mode operation when PSI_L is asserted to logic low.
The heart of the ISL6264 is the R
Robust Ripple Regulator modulator. The R
combines the best features of fixed frequency PWM and
hysteretic PWM while eliminating many of their
shortcomings. The ISL6264 modulator internally synthesizes
an analog of the inductor ripple current and uses hysteretic
comparators on those signals to establish PWM pulse
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL6264 to achieve lower
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
conventional hysteretic controllers, the ISL6264 has an error
amplifier that allows the controller to maintain a 0.5% voltage
regulation accuracy throughout the VID range from 0.75V to
1.55V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients results in
increased switching frequency, which gives the R3 regulator
a faster response than conventional fixed frequency PWM
controllers. Transient load current is inherently shared
between active phases due to the use of a common
hysteretic window voltage. Individual average phase
voltages are monitored and controlled to equally share the
static current among the active phases.
Start-up Timing
With the controller's +5V VDD voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. Approximately
100ms later, SOFT and V
VID voltage. At startup, the regulator always operates in a
2-phase CCM mode, regardless of PSI_L control signal
assertion levels. During this interval, the SOFT cap is
charged by a 43µA current source. If the SOFT capacitor is
selected to be 47nF, the SOFT ramp will be at 0.9mV/s slew
rate. Once V
approximately 7ms later, PGOOD is asserted HIGH. Typical
start-up timing is shown in Figure 28. The SOFT cap is
charged/discharged by approximate 200µA after the
start-up. Therefore, V
voltage set by the VID pins.
OUT
is within 10% of the VID voltage,
OUT
OUT
slews at about 4mV/s to the
14
begin ramping toward the final
3
Technology™, Intersil's
3
modulator
ISL6264
Static Operation
After the start sequence, the output voltage will be regulated
to the value set by the VID inputs per Table 1. The entire VID
table is presented in the AMD specification. The ISL6264 will
control the no-load output voltage to an accuracy of ±0.5%
over the range of 0.75V to 1.5V.
VID5
SOFT AND V
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VR_ON
PGOOD
V
DD
TABLE 1. V
VID4
FIGURE 28. SOFT START WAVEFORMS
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
O
100µs
VID3
ID
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
TABLE FOR AMD 6-BIT V
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
0
VID1
dV
------- -
dt
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
0
1
ª
~7.6ms
----------------
C soft
43μA
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
ID
CPU
May 28, 2009
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
1.1500
1.1250
1.1000
1.0000
0.9750
0.9500
0.9250
0.9000
VOUT
FN6359.3
(V)