ISL6264CRZ Intersil, ISL6264CRZ Datasheet - Page 21

• Manufacturer Part Number: ISL6264CRZ
• Description: IC CORE CTRLR TWO-PHASE 40-QFN
• Manufacturer: Intersil

Specifications of ISL6264CRZ

• Applications: Controller, AMD Mobile Turion™
• Voltage - Input: 5 ~ 24 V
• Number Of Outputs: 1
• Voltage - Output: 0.38 ~ 1.55 V
• Operating Temperature: -10°C ~ 100°C
• Mounting Type: Surface Mount
• Package / Case: 40-VFQFN, 40-VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Dynamic Mode of Operation - Dynamic Droop
Using DCR Sensing
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value. This could be
problematic if a load dump were to occur during this time.
This situation would cause the output voltage to rise above
the no load setpoint of the controller and could potentially
damage the CPU.
The L/DCR time constant of the inductor must be matched to
the Rn*C
Solving for C
Note, R
constant matches the C
above, the transient performance will be optimum. As in the
Static Droop Case, this process may require a slight
adjustment to correct for layout inconsistencies. For the
example of L = 0.36 H with 0.8mΩ DCR, C
shown in Equation 20:
The value of this capacitor is selected to be 330nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip (lower than the voltage required by the load line) and
slowly increases back to the steady state, the cap is too
small and vice versa. It is better to have the cap value a little
bigger to cover the tolerance of the inductor to prevent the
output voltage from going lower than the spec. This cap
-------------
DCR
C
C
FIGURE 33. LOAD LINE PERFORMANCE WITH NTC
n
n
L
2.25
2.15
2.05
=
=
2.2
2.1
=
---------------------------------- -
----------------------------------
R
-------------------------------------------------------------------
parallel 5.823k, 1.825k
R
0
O
n
n
---------------------------------- C
R
R
n
+
⋅
was neglected. As long as the inductor time
-------------
DCR
n
n
RS
time constant as shown in Equation 18:
RS
+
L
⋅
RS
n
RS
THERMAL COMPENSATION
EQV
, we now have Equation 19:
EQV
(
0.36μH
------------------- -
0.0008
EQV
EQV
20
INDUCTOR TEMPERATURE (°C)
⋅
n
n
, R
n
40
)
21
and R
=
330nF
S
time constants as given
60
n
is calculated as
80
(EQ. 18)
(EQ. 19)
(EQ. 20)
100
ISL6264
needs to be a high grade cap like X7R with low tolerance.
There is another consideration in order to achieve better
time constant match mentioned above. The NPO/COG
(class-I) capacitors have only 5% tolerance and a very good
thermal characteristics. But those caps are only available in
small capacitance values. In order to use such capacitors,
the resistors and thermistors surrounding the droop voltage
sensing and droop amplifier has to be resized up to 10X to
reduce the capacitance by 10X. But attention has to be paid
in balancing the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VID and a series impedance, in
order to achieve the 2.0mV/A load line, the impedance
needs to be 2.0mΩ. The compensation design has to target
the output impedance of the controller to be 2.0mΩ. There is
a mathematical calculation file available to the user. The
power stage parameters such as L and C
input to calculate the compensation component values.
Attention has to be paid to the input resistor to the FB pin. It
is better to keep this resistor at 1kΩ for the convenience of
OFFSET design.
Static Mode of Operation - Current Balance Using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL6264 through the
matching of the voltages present on the ISEN pins. The
ISL6264 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel's inductor. For
optimum performance, RL is chosen to be 10kΩ and CL is
selected to be 0.22µF. When discrete resistor sensing is
used, a capacitor most likely needs to be placed in parallel
with RL to properly compensate the current balance circuit.
ISL6264 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL6264 forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly equal. Take DCR current
sensing as example, two errors have to be added to find the
total current imbalance.
1. Mismatch of DCR: If the DCR has a 5% tolerance then
2. Mismatch of phase voltages/offset voltage of ISEN pins.
the resistors could mismatch by 10% worst case. If each
phase is carrying 20A then the phase currents mismatch
by 20A*10% = 2A.
The phase voltages are within 2mV of each other by
current balance circuit. The error current that results is
given by 2mV/DCR. If DCR = 1mΩ then the error is 2A.
s
are needed as the
May 28, 2009
FN6359.3