MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 10

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
TIMING CHARACTERISTICS
(DV
10
SERIAL-INTERFACE TIMING PARAMETERS (DV
SCLK Operating Frequency
SCLK Cycle Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse-Width High
SCLK Pulse-Width Low
SERIAL-INTERFACE TIMING PARAMETERS (DV
SCLK Operating Frequency
SCLK Cycle Time
DIN to SCLK Setup
DIN to SCLK Hold
SCLK Fall to Output Data Valid
CS Fall to Output Enable
CS Rise to Output Disable
CS to SCLK Rise Setup
CS to SCLK Rise Hold
SCLK Pulse-Width High
SCLK Pulse-Width Low
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DV
SPI Write to DPIO Output Valid
DPIO Rise/Fall Input to Interrupt
Asserted Delay
DPIO Input to Analog Block Delay
DIGITAL PROGRAMMABLE I/O TIMING PARAMETERS (DPIO1–DPIO4, DV
SPI Write to DPIO Output Valid
DPIO Rise/Fall Input to Interrupt
Asserted Delay
DPIO Input to Analog Block Delay
ANALOG PROGRAMMABLE I/O TIMING PARAMETERS (APIO1–APIO4, DV
SPI Write to APIO Output Valid
APIO Rise/Fall Input to Interrupt
Asserted Delay
CS to APIO4 Propagation Delay
DD
______________________________________________________________________________________
= 1.8V to 3.6V, AV
PARAMETER
DD
= 2.7V to 5.5V, T
SYMBOL
t
t
t
t
t
t
t
t
t
f
CYC
t
CSH
t
f
CYC
t
CSH
t
t
t
DCA
t
t
t
CSS
t
t
t
t
CSS
t
t
t
t
t
t
DH
DO
CH
DH
DO
CH
t
OP
DS
DV
CL
OP
DS
DV
CL
SD
DA
SD
DA
TR
TR
SD
DI
DI
DI
A
= T
From last SCLK rising edge
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
When controlling ADC, DACs, or switches
From last SCLK rising edge
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
When controlling ADC, DACs, or switches
From last SCLK rising edge
Interrupt programmed on RST1 and/or
RST2, corresponding status bits unmasked
AP4MD<1:0> = 11
MIN
DD
DD
to T
= 2.7V to 3.6V) (Figures 1 and 2)
= 1.8V to 3.6V) (Figures 1 and 2)
MAX
, unless otherwise noted.)
CONDITIONS
DD
DD
DD
= 2.7V to 3.6V, C
= 1.8V to 3.6V, C
= 2.7V to 3.6V, AV
MIN
100
50
15
15
20
20
30
30
40
40
0
0
0
0
0
0
L
L
= 20pF)
= 20pF)
DD
= 2.7V to 5.5V, C
TYP
40
50
MAX
100
150
20
20
24
24
10
40
48
48
50
55
50
50
35
L
= 20pF)
UNITS
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns