MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 60

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
The Status register is a 24-bit register that contains
Status bits from all blocks. Setting a Status bit causes
the interrupt output to assert when the corresponding
Interrupt Mask bit in the Interrupt Mask register is
cleared. If a Status bit is set and an event occurs to set
it again, the Status bit and interrupt output remain
asserted. All Status bits clear once the Status register
has been read successfully. Updating of the Status reg-
ister is delayed during a read until the Status register
read has been completed.
VM1A: 1.8V DV
0). VM1A indicates the status of the 1.8V DV
monitor. The VM1A = 1 when the DV
below the 1.8V threshold. The VM1A bit clears to 0
when the Status register is read and only if the condi-
tion is no longer true. When the 1.8V DV
monitor is powered down, the previous state of the bit is
maintained until it is read and it cannot be set to 1 in
this state.
Note: The default state is 0. However, at power-up, the
voltage monitor asserts VM1A. Read the Status register
after power-up to reset VM1A to 0.
VM1B: 2.7V DV
0). VM1B indicates the status of the 2.7V DV
monitor. VM1B = 1 when the DV
the 2.7V threshold. The VM1B bit clears to 0 when the
Status register is read and only if the condition is no
longer true. When the 2.7V DV
ered down, the previous state of the bit is maintained
until it is read and it cannot be set to 1 in this state.
Note: The default state is 0. However, at power-up, the
voltage monitor asserts VM1B. Read the Status register
after power-up to reset VM1B to 0.
Table 31. DPIO_ Mode Bit Configuration (continued)
60
D P_ M D 3 D P_ M D 2 D P_ M D 1 D P_ M D 0
1
1
1
______________________________________________________________________________________
1
1
1
DD
DD
Voltage-Monitor Status bit (default =
Voltage-Monitor Status bit (default =
0
1
1
DD
DD
1
0
1
voltage monitor is pow-
voltage drops below
DD
MAX1329
Status Register
SPDT2
DRDY
GPO
voltage drops
DD
DD
DD
MODE
voltage
voltage
voltage
MAX1330
SPDT2
DRDY
GPO
Digital input. SPDT2 controls the SPDT2 switch. See the Switch
Control Register section.
Digital output. DRDY goes high when a conversion is complete
and valid ADC data is available in the ADC Data register. If the
ADC Data or Status register is read, DRDY returns low. If high,
DRDY pulses low for one ADC master clock cycle while
updating the ADC Data register before returning high.
Digital output. Write to the DP_LL register bits to set the GPO
level.
VM2: AV
VM2 indicates the status of the AV
VM2 = 1 when the AV
threshold programmed by the VM2CP<2:0> bits. VM2
clears to 0 when the Status register is read and only if
the condition is no longer true. When the AV
monitor is powered down, the previous state of the bit is
maintained until it is read and it cannot be set to 1 in
this state.
ADD: ADC Done Status bit (default = 0). The ADD bit
indicates when an ADC conversion has completed and
the data is ready to be read from the ADC Data regis-
ter. ADD is set to 1 after the data from an ADC conver-
sion has been written to the ADC Data register. ADD
clears to 0 when the Status register or the ADC Data
register is read.
AFF: ADC FIFO Full Status bit (default = 0). The AFF bit
indicates that the ADC has written data to the ADC
FIFO address programmed by the AFFI<3:0> bits. The
AFF bit is set to 1 when the address has been written.
AFF clears to 0 when the Status register is read or when
the ADC FIFO register is read (any number of ADC data
words) or written.
ACF: ADC Accumulator Full Status bit (default = 0). The
ACF bit indicates that the programmed number of ADC
conversion results have been accumulated. The result
is saved in the ACCDATA<19:0> bits in the ADC
Accumulator register for the next programmed number
of accumulations before it is overwritten. The ACF bit
sets to 1 when the ADC Accumulator is filled to the pro-
grammed address. The ACF bit clears to 0 when the
Status register is read or when the ADC Accumulator
register is read or written.
DD
Voltage-Monitor Status bit (default = 0).
DESCRIPTION
DD
voltage drops below the
DD
voltage monitor.
DD
voltage