MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 59

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 31. DPIO_ Mode Bit Configuration
D P_ M D 3 D P_ M D 2 D P_ M D 1 D P_ M D 0
12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
______________________________________________________________________________________
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
MAX1329
CONVST
SPDT1
SHDN
DSWA
DSWB
OSW1
DLDA
DLDB
DLAB
WUL
WUH
SLP
GPI
MODE
MAX1330
CONVST
SPDT1
DSWA
SHDN
OSW2
OSW1
DLAB
DLDA
WUH
WUL
SLP
GPI
—
hi g h on SLP tr ansfer s the p ow er contr ol b ack to the r eg i ster
setti ng s. S ee the C l ock C ontr ol Reg i ster secti on.
Digital input. DPIO_ logic-level read from DP_LL register bit.
Digital input. A falling edge on WUL sets the OSCE bit enabling
the oscillator.
Digital input. A rising edge on WUH sets the OSCE bit enabling
the oscillator.
D i g i tal i np ut. A l og i c- l ow on SLP over r i d es the r eg i ster setti ng s and
p ow er s d ow n al l ci r cui ts excep t V M 1 and al l the r eg i ster s. A l og i c-
Digital input. A logic-low on SHDN overrides the register
settings and powers down all circuits. A logic-high on SHDN
transfers the power control back to the register settings.
Digital input. A rising edge on DLAB shifts DACA and DACB
data from the input register to the output register or sequences
through FIFOA if enabled. For the MAX1330, this applies only
to DACA.
Digital input. CONVST controls acquisition time and conversion
start. A falling edge on CONVST puts the ADC in acquisition
mode. A rising edge on CONVST starts a single conversion.
Digital input. A rising edge on DLDA shifts DACA data from the
input to output register or sequences through FIFOA if enabled.
Digital input. DSWA and OSW3 control the DACA and op amp 3
switches, respectively. See the Switch Control Register section.
Digital input. A rising edge on DLDB shifts DACB data from the
input to output register.
Digital input. DACB and op amp 2 control the DACB and op
amp 2 switches, respectively. See the Switch Control Register
section.
Digital input. Op amp 1 switch control. See the Switch Control
Register section.
Digital input. SPDT1 controls the SPDT1 switch. See the Switch
Control Register section.
DESCRIPTION
59