MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 40

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
The ADC Control register configures the autoconvert
mode, the ADC power-down modes, the ADC reference
buffer, and the internal reference voltage. Changes
made to the ADC Control register settings are applied
immediately. If changes are made during a conversion
in progress, discard the results of that conversion to
ensure a valid conversion result.
AUTO<2:0>: ADC Autoconvert bits (default = 000). The
AUTO<2:0> bits configure the ADC to continuously con-
vert at the selected interval (see Table 4). Calculate the
conversion rate by dividing the ADC master clock fre-
quency by the selected number of clock cycles. For
example, if the ADC master clock frequency is
3.6864MHz and the selected value is 256, the conversion
rate is 3.6864MHz/256 or 14.4ksps. The conversion can
be started with the ADC Direct Write command and runs
continuously using the ADC master clock. Write 000 to
the AUTO<2:0> bits to disable autoconvert mode. When
the autoconvert ADC master clock cycle rate is set to 32
and the acquisition time is set to 32 (AUTO<2:0> = 001,
ACQCK<1:0> = 11, and GAIN<1:0> = 1X), the acquisi-
tion time is automatically reduced to 16 clocks so that the
ADC throughput is less than the autoconversion interval.
The automode operation is unavailable in burst mode.
APD<1:0>: ADC Power-Down bits (default = 00). The
APD<1:0> bits control the power-down states of the
ADC and PGA (see Table 5). When a direct-mode ADC
conversion command is received, the ADC and PGA
power up except when APD<1:0> = 00.
Table 3. Register Summary (continued)
Note: R/W = 0 for write, R/W = 1 for read, X = don’t care.
* Data length can vary from 1 to 16 words, where a word is 16 bits (12 data bits plus 4 address bits).
40
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reset
NAME
DEFAULT
REGISTER
______________________________________________________________________________________
NAME
AUTO2
MSB
START
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
READ/
WRITE
(R/W)
Register Bit Descriptions
AUTO1
W
X
X
X
X
X
X
0
ADC Control Register
1
1
1
1
1
1
1
(ADR<4:0>)
ADDRESS
1
1
1
1
1
1
1
AUTO0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
APD1
X
0
The burst mode outputs data to DOUT directly in real
time as the bit decision is made on the falling edge of
SCLK and the latest conversion result is also stored in
the ADC Data register. For this mode, the conversion
rate is controlled by the SCLK frequency, which is limited
to 5MHz. If the charge pump is enabled, synchronize
SCLK with the CLKIO clock to prevent charge-pump
noise from corrupting the ADC result. Initiate the conver-
sion by writing to the ADC Control register. SCLK is
required to run continuously during the conversion peri-
od. For ADC gains of 1 or 2, a total of 14 to 28 clocks
(two to 16 for acquisition and 12 for conversion) are
required to complete the conversion. For ADC gains of 4
or 8, a total of 16 to 44 clocks (four to 32 for acquisition,
and 12 for conversion) are required to complete the con-
version. Bringing CS high aborts burst mode.
AREF<1:0>: ADC Reference Buffer bits (default = 00).
The AREF<1:0> bits set the ADC reference buffer gain
when REFE = 0 and the REFADC output voltage when
REFE = 1 (see Table 6). Set AREF<1:0> to 00 to dis-
able the ADC reference buffer and drive REFADC
directly with an external reference.
REFE: Internal Reference Enable bit (default = 0). REFE
= 1 enables the internal reference and sets REFADJ to
2.5V. REFE = 0 disables the internal reference, allowing
an external reference to be applied at REFADJ, which
drives the inputs to the ADC and DAC reference
buffers. The voltage at REFADJ is also used for temper-
ature measurement and must be 2.5V for accurate
results. See the Temperature Sensor section. This bit is
mirrored in the DAC Control register so that writing
either location updates both bits.
X
(D<255:0>, D<23:0>, D<15:0>, OR D<7:0>)
APD0
0
X
RESERVED, DO NOT USE
RESERVED, DO NOT USE
RESERVED, DO NOT USE
RESERVED, DO NOT USE
RESERVED, DO NOT USE
RESERVED, DO NOT USE
X
AREF1
DATA
0
X
AREF0
X
0
X
REFE
LSB
0
X