MAX1329BETL+ Maxim Integrated Products, MAX1329BETL+ Datasheet - Page 24

• Manufacturer Part Number: MAX1329BETL+
• Description: IC DAS 12BIT 300KSPS 40-TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX1329BETL+

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12-/16-Bit DASs with ADC, DACs, DPIOs, APIOs,
Reference, Voltage Monitors, and Temp Sensor
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MAX1329
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PIN
MAX1330
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REFDAC
REFADC
REFADJ
NAME
AGND
DGND
CLKIO
OUTA
SNC2
SCM2
SNO2
DV
AV
AIN2
AIN1
FBA
C1B
C1A
EP
DD
DD
DACA Force-Sense Output. Also internally connected to ADC mux.
DACA Force-Sense Feedback Input. Also internally connected to ADC mux.
DAC Internal Reference Buffer Output/DAC External Reference Input. In internal reference
mode, REFDAC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In
external DAC reference buffer mode, disable internal reference buffer. Bypass REFDAC to
AGND with a 1µF capacitor.
Analog Switch 2 Normally-Closed Terminal
Analog Switch 2 Common Terminal
Analog Switch 2 Normally-Open Terminal
Analog Input 2. Also internally connected to ADC mux.
Analog Input 1. Also internally connected to ADC mux.
ADC Internal Reference Buffer Output/ADC External Reference Input. In internal reference
mode, REFADC provides a 1.25V, 2.048V, or 2.5V internal reference buffer output. In
external ADC reference buffer mode, disable internal reference buffer. Bypass REFADC to
AGND with a 1µF capacitor.
Internal Reference Output/Reference Buffer Amplifiers Input. In internal reference mode,
bypass REFADJ to AGND with a 0.01µF capacitor. In external reference mode, disable
internal reference.
Analog Ground
Analog Supply Input. Bypass AV
charge pump enabled, see Table 32 for required capacitor values.
Charge-Pump Capacitor Input B. Connect C
required capacitor values.
Charge-Pump Capacitor Input A. Connect C
required capacitor values.
Digital Supply Input. Bypass DV
charge pump, see Table 32 for required capacitor values.
Digital Ground
Clock Input/Output. In internal clock mode, enable CLKIO output for external use. In
external clock mode, apply a clock signal at CLKIO for the ADC and charge pump.
Exposed Pad. The exposed pad is located on the package bottom and is internally
connected to AGND. Connect EP to the analog ground plane. Do not route any PCB traces
under the package.
DD
DD
to DGND with at least a 0.01µF capacitor. When using
to AGND with at least a 0.01µF capacitor. With the
FUNCTION
Pin Description (continued)
FLY
FLY
across C1A and C1B. See Table 32 for
across C1A and C1B. See Table 32 for