DS1865T+T&R Maxim Integrated Products, DS1865T+T&R Datasheet - Page 12

IC PON CONTROL TRI 28-TQFN

DS1865T+T&R

Manufacturer Part Number
DS1865T+T&R
Description
IC PON CONTROL TRI 28-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1865T+T&R

Applications
*
Mounting Type
Surface Mount
Package / Case
28-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PON Triplexer Control and
Monitoring Circuit
bias update comparison was above the APC set point,
and checks LTXP to see if the last bias update compari-
son was below the APC set point. Depending on the
results of the comparison, the corresponding alarms
and warnings (TXP-HI, TXP-LO) are asserted or
deasserted.
The DS1865 has a programmable comparator sample
time based on an internally generated clock to facilitate a
wide variety of external filtering options suitable
for burst-mode transmitter data rates between 155Mbps
and 1250Mbps. The rising edge of the burst enable
(BEN) triggers the sample to occur, and the Update Rate
register (Table 02h, Register 88h) determines the sam-
pling time. The first sample occurs t
12
Figure 1. Power-Up Timing
Figure 2. TX-D Timing (Normal Operating Conditions)
TX-D
V
____________________________________________________________________
I
MOD
BIAS
t
t
OFF
OFF
SAMPLE
V
BIAS
I
MOD
V
BIAS
CC
t
t
ON
ON
V
POA
t
INIT
I
STEP
FIRST
2x I
STEP
3x I
after the rising
1
STEP
4x I
2
STEP
3
4
edge of BEN. The internal clock is asynchronous to BEN,
causing a ±50ns uncertainty regarding when the first
sample will occur following BEN. After the first sample
occurs, subsequent samples occur on a regular interval,
t
Table 2. Update Rate Timing
*All codes greater than 1001b (1010b–1111b) use the maximum
sample time of code 1001b.
5
t
REP
SEARCH
SR
1001b*
. Table 2 shows the sample rate options available.
0000b
0001b
0010b
0011b
0100b
0101b
0110b
0111b
1000b
6
3
–SR
BINARY SEARCH
7
0
8
FIRST SAMPLE
MINIMUM TIME
FROM BEN TO
(t
9
FIRST
1350ns
1550ns
1750ns
2150ns
2950ns
3150ns
350ns
550ns
750ns
950ns
10
) ±50ns
11
INTEGRATOR
APC
ON
12
FOLLOWING FIRST
SAMPLE PERIOD
13
SAMPLE (t
REPEATED
1200ns
1600ns
2000ns
2800ns
3200ns
3600ns
4400ns
6000ns
6400ns
800ns
REP
)

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