DS1865T+T&R Maxim Integrated Products, DS1865T+T&R Datasheet - Page 56

IC PON CONTROL TRI 28-TQFN

DS1865T+T&R

Manufacturer Part Number
DS1865T+T&R
Description
IC PON CONTROL TRI 28-TQFN
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS1865T+T&R

Applications
*
Mounting Type
Surface Mount
Package / Case
28-TQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PON Triplexer Control and
Monitoring Circuit
56
Table 02h, Register B8h: FETG Enable
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
Configures the maskable interrupt for the FETG pin.
____________________________________________________________________
B8h
TEMP EN
bit1:0
bit7
bit6
bit5
bit4
bit3
bit2
bit7
TEMP EN: Enables/disables active interrupts on the FETG pin due to temperature measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
V
threshold limits.
0 = Disable (Default).
1 = Enable.
MON1 EN: Enables/disables active interrupts on the FETG pin due to MON1 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON2 EN: Enables/disables active interrupts on the FETG pin due to MON2 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON3 EN: Enables/disables active interrupts on the FETG pin due to MON3 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
MON4 EN: Enables/disables active interrupts on the FETG pin due to MON4 measurements
outside the threshold limits.
0 = Disable (Default).
1 = Enable.
RESERVED (Default = 0)
V
CC
CC
00h
PW2
PW2
Nonvolatile (SEE)
EN: Enables/disables active interrupts on the FETG pin due to V
EN
1
(FETG EN
MON1 EN
1
)
MON2 EN
MON3 EN
MON4 EN
CC
measurements outside the
RESERVED
RESERVED
bit0

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