DS1865T+T&R Maxim Integrated Products, DS1865T+T&R Datasheet - Page 61

• Manufacturer Part Number: DS1865T+T&R
• Description: IC PON CONTROL TRI 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1865T+T&R

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 02h, Register C1h to C3h: Reserved
FACTORY DEFAULT:
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
These registers are reserved.
Table 02h, Register C4h: DAC1
FACTORY DEFAULT:
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
Register to control DAC1.
Table 02h, Register C0h: DPU
FACTORY DEFAULT
READ ACCESS
WRITE ACCESS
MEMORY TYPE:
Controls the power-on values for D3, D2, D1, and D0 output pins and mux and invertion of the LOSI pin.
C4h
C0h
RESERVED
Bit7:6
bit7
Bit5
Bit4
Bit3
Bit2
bit1
bit0
bit7
2
7
RESERVED
RESERVED
INV LOSI: Inverts the buffered input pin LOSI to output pin D0 if MUX LOSI is set. If MUX LOSI is not
set then this bit’s value is a don’t care.
0 = (Default) noninverted LOSI to D0 pin.
1 = Inverted LOSI to D0 pin.
MUX LOSI: chooses the control for D0 output pin.
0 = (Default) DO is controlled by bit D0 OUT found in Lower Memory, Register 78h.
1 = LOSI is buffered to D0 pin.
D3 CNTL: At power-on, this value is loaded into bit D3 OUT of Lower Memory, Register 78h to
control the output pin D3.
D2 CNTL: At power-on, this value is loaded into bit D2 OUT of Lower Memory, Register 78h to
control the output pin D2.
D1 CNTL: At power-on, this value is loaded into bit D1 OUT of Lower Memory, Register 78h to
control the output pin D1.
D0 CNTL: At power-on, this value is loaded into bit D0 OUT of Lower Memory, Register 78h to
control the output pin D0.
0000 0000h
PW2
PW2
00h
PW2
PW2
00h
PW2
PW2
Nonvolatile (SEE)
Nonvolatile (SEE)
Nonvolatile (SEE)
2
6
____________________________________________________________________
INV LOSI
2
5
PON Triplexer Control and
MUX LOSI
2
4
D3 CNTL
2
3
Monitoring Circuit
D2 CNTL
2
2
D1 CNTL
2
1
D0 CNTL
bit0
bit0
2
0
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