DS1865T+T&R Maxim Integrated Products, DS1865T+T&R Datasheet - Page 20

• Manufacturer Part Number: DS1865T+T&R
• Description: IC PON CONTROL TRI 28-TQFN
• Manufacturer: Maxim Integrated Products

Specifications of DS1865T+T&R

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 28-TQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PON Triplexer Control and
Monitoring Circuit
Writing a Single Byte to a Slave: The master must
generate a START condition, write the I
byte (R/W = 0), write the byte of data, and generate a
STOP condition. The master must read the slave’s
acknowledgement during all byte write operations.
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condi-
tion, writes the slave address byte (R/W = 0), writes the
memory address, writes up to 8 data bytes, and gener-
ates a STOP condition. The DS1865 writes 1 to 8 bytes
(1 page or row) with a single write transaction. This is
internally controlled by an address counter that allows
data to be written to consecutive addresses without
transmitting a memory address before each data byte is
sent. The address counter limits the write to one 8-byte
page (one row of the memory map). Attempts to write to
additional pages of memory without sending a STOP
condition between pages result in the address counter
wrapping around to the beginning of the present row.
Example: A 3-byte write starts at address 06h and
writes three data bytes (11h, 22h, and 33h) to three
“consecutive” addresses. The result is that addresses
06h and 07h contain 11h and 22h, respectively, and
the third data byte, 33h, is written to address 00h.
To prevent address wrapping from occurring, the mas-
ter must send a STOP condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new START
20
Figure 9. I
SDA
SCL
NOTE: TIMING IS REFERENCED TO V
____________________________________________________________________
2
C Timing Diagram
STOP
t
BUF
START
IL(MAX)
I
t
HD:STA
2
t
LOW
C Communication
AND V
IH(MIN)
.
2
t
R
t
HD:DAT
C slave address
t
F
t
HIGH
t
SU:DAT
condition, and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
Acknowledge Polling: Any time an EEPROM location
is written, the DS1865 requires the EEPROM write time
(t
the byte of data to EEPROM. During the EEPROM write
time, the device does not acknowledge its slave
address because it is busy. It is possible to take advan-
tage of that phenomenon by repeatedly addressing the
DS1865, which allows the next page to be written as
soon as the DS1865 is ready to receive the data. The
alternative to acknowledge polling is to wait for a maxi-
mum period of t
again to the DS1865.
EEPROM Write Cycles: When EEPROM writes occur
to the memory, the DS1865 writes to all three EEPROM
memory locations, even if only a single byte was modi-
fied. Because all three bytes are written, the bytes that
were not modified during the write transaction are still
subject to a write cycle. This can result in all three bytes
being worn out over time by writing a single byte
repeatedly. The DS1865’s EEPROM write cycles are
specified in the Nonvolatile Memory Characteristics
table. The specification shown is at the worst-case tem-
perature. It can handle approximately 10 times that
many writes at room temperature. Writing to SRAM-
shadowed EEPROM memory with SEEB = 1 does not
count as an EEPROM write cycle when evaluating the
EEPROM’s estimated lifetime.
W
) after the STOP condition to write the contents of
REPEATED
START
t
SU:STA
t
HD:STA
W
to elapse before attempting to write
t
SP
t
SU:STO