MC33780EG Freescale Semiconductor, MC33780EG Datasheet - Page 16

• Manufacturer Part Number: MC33780EG
• Description: IC DBUS MASTER DUAL DIFF 16-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33780EG

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the Idle drivers or Signal drivers as is appropriate. A
comparator in the Control block compares the DnL output
voltage with the internal Signal high voltage to determine the
transition from Idle driver to Signal driver. The overvoltage
signal modifies the driver characteristics. This is described in
more detail in the
DSIS signal to the DBUS differential signal voltage levels.
This differential signal is buffered and slew rate controlled by
the Signal drivers. This block is active in all driver modes.
a low common mode voltage. This is especially important
during the Idle to Signal transition in order to produce a
smooth changeover to the Signal driver. This is accomplished
by monitoring the common mode voltage and modifying the
Idle driver slew rates. This is the function of the Common
Mode Correction block. An additional feature to make a
smooth changeover and minimize undershoot is to reduce
the slew rate as the changeover point is approached. This
block is not illustrated in
output detects the Slave device response current. A
comparator (Comp.) generates the signal DSIR that is
supplied to the logic.
(V
the logic signal (DSIR). The sense amplifier is a ‘gm’ stage
that amplifies the voltage across the sense resistor (R
produce an output current that charges and discharges a filter
capacitor. The voltage across the filter capacitor is compared
16
33780
FUNCTIONAL DESCRIPTIONS
FUNCTIONAL INTERNAL BLOCK DESCRIPTION
OS
The DSIF signal controls the state of the drivers, enabling
The overtemperature signal is also applied to this block.
The Differential Signal Generation block converts the
A special requirement of the differential bus is to maintain
A sense resistor between the Signal driver and the DnH
The comparator consists of a sense amplifier with offset
), a filter capacitor and logic gate with buffers to produce
Load Dump Operation
Figure
10.
section.
S
) to
with the threshold voltage of the logic gate to produce the
output signal. The voltage across the filter capacitor is
clamped between VCC and ground. See
Definitions
product of the overdrive current (I
the interference pulse, which must be less than 1.7 µs * mA
for the interference to be filtered.
•C = value of filter capacitor = 2.0 pF
•V
•A = current gain from sense resistor to filter capacitor =
•I
•I
The filter delay time is given by:
The filter characteristic can also be expressed as the
BUS
TH
V
TH
I
output current of ± 40 µA)
O
OS
[mA] = response current threshold = V
/ I
[mA] = bus response current.
= threshold of logic gate = V
BUS
t [µs] = (C * V
= 3.0 µA/mA (the amplifier saturates with an
Figure 11. Receive Filter
R
S
TH
Analog Integrated Circuit Device Data
) / A (I
gm
BUS
BUS
- I
TH
I
Freescale Semiconductor
I
BUS
O
CC
- I
) = 1.7 / (I
C
TH
/2 = 2.5 V
) and the duration of
Figure
V
TH
OS
BUS
/R
11.
S
- I
TH
= 6
)
DnH
DSIR