MC33780EG Freescale Semiconductor, MC33780EG Datasheet - Page 29

• Manufacturer Part Number: MC33780EG
• Description: IC DBUS MASTER DUAL DIFF 16-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33780EG

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DnL REGISTERS
registers, one for each of the buses. When written to, the data
is the low byte of a 16-bit command. When read, it is the
D01STAT REGISTER
of DBUS 0 and 1. The values are latched when
asserted low. Any changes of the status that these bits detect
ERn–CRC Error Bit for Channel n
receive FIFO, so each FIFO entry has a bit to indicate
whether the data in that stage of the FIFO was received
correctly.
and DnL registers, the associated CRC error status is
available at ERn in the D01STAT register. When a new data
value becomes available owing to a pop (read) of a previous
value, the ERn status flag reflects the CRC status of the new
data value. There is no separate interrupt associated with
ERn because it is always associated with the RFNEn status
flag.
TFEn–Transmit FIFO Empty Bit for Channel n
bursts may be used to fill the FIFO without checking the flags
between writes.
Analog Integrated Circuit Device Data
Freescale Semiconductor
SPI Data Bit
Read / Write
Reset
SPI Data Bit
Read
Reset
These are read / write registers. There are two of these
This is a read-only register. This register covers the status
• 0 = CRC value for the data in the read buffer was correct
• 1 = CRC value for the data in the read buffer was not
CRC errors are associated with each data value in the
Whenever a received data value is available in the DnH
• 0 = Transmit FIFO not empty.
• 1 = Transmit FIFO empty.
When the transmit FIFO is empty, four consecutive write
and no overcurrent condition exists.
correct (data not valid) or that an overcurrent event has
occurred.
INT
will be asserted on the transmit FIFO
Bit 7
Bit 7
Bit 7
ER1
0
0
Figure 27. Channel 1 and 2 Status Register Bit Assignments
TFE1
Bit 6
6
0
6
1
Figure 26. DnL Data Register Bit Assignments
TFNF1
Bit 5
5
0
5
1
CS
is
RFNE1
Bit 4
4
0
4
0
register initiates a DBUS transaction. The bit assignments
are shown in
asserted. This is done to ensure that partial updates will not
occur. The bit assignments are shown in
.
empty condition if TIEn is set.
TIEn is cleared or a byte is written to DnL.
TFNFn–Transmit FIFO Not Full Bit for Channel n
full condition. When the conclusion of a transfer frame would
cause both TFNF and RFNE to become set, RFNE becomes
set but TFNF is not set until one clock cycle later. When the
transmit FIFO is full, attempts to write more data into the
FIFO are ignored.
RFNEn–Receive FIFO Not Empty Bit for Channel n
not possible to get more than four transmit messages into the
system at a time. When there is any data in the receive FIFO,
a write to the transmit buffer also pops data from the receive
FIFO. If RIEn is set, INT will be asserted if this bit is set and
data becomes available in the receive buffers.
low byte of a 16-bit return on the DBUS. Writing to this
Bit 3
ER0
3
0
3
0
.
will not be transferred to the register until
• 0 = Transmit FIFO full; no more room for additional
• 1 = Transmit FIFO not full; there is room for more data
There is no interrupt associated with the transmit FIFO not
• 0 = No new data ready.
• 1 = One or more data entries in the receive FIFO; data
It is not possible to overflow the receive FIFO because it is
data.
in the transmit FIFO.
is available to be read.
TFE0
Bit 2
Figure 26
2
0
2
1
TFNF0
LOGIC COMMANDS AND REGISTERS
Bit 1
1
0
1
1
FUNCTIONAL DEVICE OPERATION
INT
will be de-asserted when
RFNE0
Bit 0
0
0
0
0
Figure 27
CS
is de-
33780
29