MC33780EG Freescale Semiconductor, MC33780EG Datasheet - Page 19

• Manufacturer Part Number: MC33780EG
• Description: IC DBUS MASTER DUAL DIFF 16-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33780EG

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI COMMUNICATIONS
followed by 1 or more bytes of data. The start of an SPI
transaction is signaled by
sent (bit 7) of the first byte signals a read or write (write = 1)
of data. The last five bits (bits 4 – 0) of the command set a
writes the low data register (DnL). The Control and Status
registers can be read without affecting the receive FIFO. The
transmit FIFO is popped at the end of the DBUS transaction.
example assumes the last SPI transaction read or wrote the
data from register 00011 and is now pointing at 00100
(D01STAT). During the first byte of the SPI transaction, the
first MOSI bit is 1 (write) and the last five are 00000. During
this command byte, MISO returns the data from register
00100 (D01STAT). During the next SPI transactions, MOSI
DBUS COMMUNICATIONS
registers. A CRC pattern is automatically appended to each
(DSIF), a data signal (DSIS), and a data return (DSIR) signal.
These are signals internal to the IC associated with the
protocol engine.
which marks the start of a frame. There is a one bit-time delay
before the MSB of data appears on the DSIS pin. Data bits
start with a falling edge on DSIS. The low time is 1/3 of the bit
time for a 1, and 2/3 of a bit time for a 0. Data is transmitted
on DSIS and received on DSIR pins simultaneously. Receive
data is the captured level on the DSIR pin at the end of each
Analog Integrated Circuit Device Data
Freescale Semiconductor
MOS I
MI SO
SCLK
C L K
C SB
All SPI transactions start with a command byte and can be
The receive FIFO is popped only when the SPI reads or
Figure 14
The DBUS messages contain data from the DnH and DnL
DBUS Driver/Receiver communications involve a frame
A message starts with a falling edge on the DSIF signal,
CS
Bit 7
R/W
Bit n
W R IT E CO MM AN D
D SI 01 ST A T( 00 10 0)
P O IN T T O 00 00 0
shows an example of a write operation. This
WRITE COMMAND
D01STAT (00100)
POINT TO 00000
D AT A F R O M
DATA FROM
X
6
. . . . . . . . . . . . . . . .
CS
being asserted low. The first bit
X
5
Figure 13. SPI Communications, First Byte of Burst Transfer
DA T A TO DS I0 H
DATA FROM D0H
D SI 0H ( 00 000 )
DATA TO D0H
D AT A F R O M
FUNCTIONAL DEVICE OPERATION
( 00 00 0)
(00000)
(00000)
ADDR4
Figure 15. DBUS Communications Message
LOGIC COMMANDS AND REGISTERS
4
Figure 14. SPI Burst Transfer Example
ADDR3
Bit 0
3
D AT A T O DSI 0L
DATA FROM D0L
D SI0 L (0 00 01 )
DATA TO D0L
DA T A FR OM
(00 00 1)
(00001)
(00001)
ADDR2
CRC n
2
pointer to the desired register. Bits 5 and 6 are unused. See
Figure
sent over the SPI will be a read / write of data to the sequential
next register. After address 10101 is written to, the next write
will wrap around to address 00000.
updates the data in register 00000 with new data while
reading back the old data via MISO.
occurring at the same time, the changes caused earlier
during the same burst would not be reflected by the data
returned, because the D01STAT is latched at
is set), the D0H register is skipped in the sequence. The
same is true for the D1H register when MS1 is set and
SWLEN1 = 1000.
message. The data and CRC lengths are programmed by the
DnLENGTH register.
DBUS message.
bit time. At the end of the bit time for the last CRC bit, the
DSIF pin returns to a logic high (Idle level). A minimum delay
is imposed between successive frames as determined by the
DnCTRL register.
from the MCU) to the low byte of the data register (DnL).
When 9- to 16-bit messages are to be sent, the user writes to
the DnH register first and then the DnL register before the
combined 9 to 16-bit data value DnH:DnL is sent on the
DBUS. The user should first check the TFNFn status flag to
be sure the transmit FIFO is not full before writing a new data
Although it looks like the read and write for an address are
When a short word is selected for Bus 0 (MS0 in D0CTRL
Users initiate a message by writing (via the SPI interface
13. As long as
ADDR1
. . . . .
1
D AT A T O D SI 1H
DATA FROM D1H
DS I1H ( 0 001 0)
DATA TO D1H
D AT A F RO M
(0 00 10 )
(00010)
(00010)
ADDR0
CRC 0
CS
Figure 15
0
LOGIC COMMANDS AND REGISTERS
is asserted low, each additional byte
FUNCTIONAL DEVICE OPERATION
shows the structure of the
DA T A TO D SI1 L
DATA FROM D1L
D SI 1L (00 01 1)
D AT A F R O M
DATA TO D1L
(0 00 11 )
(00011)
(00011)
CS
going low.
33780
19