MC33780EG Freescale Semiconductor, MC33780EG Datasheet - Page 33

• Manufacturer Part Number: MC33780EG
• Description: IC DBUS MASTER DUAL DIFF 16-SOIC
• Manufacturer: Freescale Semiconductor

Specifications of MC33780EG

• Applications: *
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.300", 7.5mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DEV[1:0]–Spread Spectrum Frequency Deviation for
Channel n
spectrum signalling. DEV [1:0] is recommended to be
programmed to either 10 or 11 whenever the spread
spectrum is enabled. DEV = “00” (the default) and DEV = “01”
(typical 1000 nsec) are optionally available under application
usage.
the updating of the PLL loop center frequency. After reset or
when either of these registers is written to, the spread
spectrum PLL loop goes into fast acquisition mode for 64
cycles. After this, the PLL switches to slow acquisition mode.
minimum data rate available.
loop up/down counter. This 6-bit value is the control input to
the Center Frequency DAC of
normalized to the center frequency of the PLL.A write to the
register will be ignored. The 6-bit SSUD value will be latched
Analog Integrated Circuit Device Data
Freescale Semiconductor
SPI Data Bit
Read/Write
Reset
SPI Data Bit
Read/Write
Reset
SPI Data Bit
Read
Reset
SPI Data Bit
Read
Reset
These bits control the frequency deviation of the spread
DEV[1 : 0] = 10 = Deviation enabled.
DEV[1 : 0] = 11 = Deviation disabled.
The OFFSETH[0] and OFFSETL[7:0] register bits control
The default value of 0 0000 0000 sets the PLL to the
The SSUD[5:0] value reflects the current state of the PLL
OFFSETL7 OFFSETL6 OFFSETL5 OFFSETL4 OFFSETL3 OFFSETL2 OFFSETL1 OFFSETL0
Bit 7
Bit 7
Bit 7
Bit 7
–
0
0
0
0
0
0
Figure 34. Dn Spread Spectrum Offset High Register Bit Assignments
Figure 35. Dn Spread Spectrum Offset Low Register Bit Assignments
Figure 36. D0 Spread Spectrum Up / Down Register Bit Assignments
Figure 37. Dn Spread Spectrum Up / Down Register Bit Assignments
Figure
6
–
0
6
0
6
0
0
6
0
0
12. This 6-bit value is
SSUD5
SSUD5
5
–
0
5
0
5
1
5
1
SSUD4
SSUD4
4
–
0
4
0
4
0
4
0
SSUD3
SSUD3
fine control of the bit rate without frequency spreading.
DnOFFSETH and DnOFFSETL REGISTERS
PLL offset value. There are four of these registers, two for
each DBUS channel. The bit assignments are shown in
Figure 34
DnSSUD Registers
loop 6-bit update count. There are two of these registers, one
for each DBUS channel. The bit assignments are shown in
Figure 36
hardwired to logic 1. This bit is a 1 regardless of the state of
the spread-spectrum control bits in DOSSCTRL.
whenever CS transitions low so that the value of SSUD will
not change during an SPI command.
its range to minimize the PLL acquisition time.
3
–
0
3
0
3
0
3
0
The mode with deviation disabled may be used to achieve
These read/write registers control the spread spectrum
These read-only registers reflect the spread spectrum PLL
D0SSUD also contains an ID bit in D0SSUD[2] which is
The default value of 10 0000 puts the VCO at the center of
and
and
SSUD2
ID
2
–
0
2
0
2
1
2
0
Figure
Figure 37.
35.
SSUD1
SSUD1
LOGIC COMMANDS AND REGISTERS
1
–
0
1
0
1
0
1
0
FUNCTIONAL DEVICE OPERATION
OFFSETH8
SSUD0
SSUD0
0
0
0
0
0
0
0
0
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