MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 10

• Manufacturer Part Number: MT18LSDT6472G-13ED2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 4831838208
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Commands
able commands. This is followed by a written descrip-
tion of each command.
Table 9:
Note: 1; notes appear below table)
NOTE:
1. CKE is HIGH for all commands shown except Self Refresh.
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
2. A0–A11 (128MB and 256MB), A0–A12 (512MB) define the op-code written to the Mode Register, and should be
3. A0–A11 (128MB and 256MB), A0–A12 (512MB) provide device row address. BA0, BA1 determine which device bank is
4. A0–A9 provide device column address for 128MB module; A0–A9/A11 for 256MB and 512MB modules; A10 HIGH
5. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: both device banks are precharged
6. This command is Auto Refresh if CKE is HIGH, Self Refresh if CKE is LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay).
COMMAND INHIBIT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or
SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
Write Enable/Output Enable
Write Inhibit/Output High-Z
The Truth Table provides a quick reference of avail-
driven low.
made active.
enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1
determine which device bank is being read from or written to.
and BA0, BA1 are “Don’t Care.”
Truth Table – SDRAM Commands and DQMB Operation
NAME (FUNCTION)
For a more detailed
CS#
H
L
L
L
L
L
L
L
L
–
–
168-PIN REGISTERED SDRAM DIMM
10
128MB, 256MB, 512MB (x72, ECC)
description of commands and operations refer to the
64Mb,
datasheets.
RAS# CAS# WE# DQMB
X
H
H
H
H
L
L
L
L
–
–
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128Mb,
X
H
H
H
H
L
L
L
L
–
–
H
H
H
H
X
L
L
L
L
–
–
or
L/H
L/H
256Mb
H
X
X
X
X
X
X
X
L
8
8
Bank/Row
Bank/Col
Bank/Col Valid
Op-Code
ADDR
Code
SDRAM
X
X
X
X
–
–
©2003, Micron Technology Inc.
Active
Active
High-Z
DQS
X
X
X
X
X
X
X
component
NOTES
6, 7
3
4
4
5
2
8
8