MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 7

• Manufacturer Part Number: MT18LSDT6472G-13ED2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 4831838208
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

module), select the device row. The address bits A0-A9
(for 64MB) or A0-A9, A11 (for the 256MB and 512MB
module), registered coincident with the READ or
WRITE command are used to select the starting device
column location for the burst access.
tialized. The following sections provide detailed infor-
mation
definition, command descriptions and device opera-
tion.
Initialization
predefined manner. Operational procedures other
than those specified may result in undefined opera-
tion. Once power is applied to Vdd and VddQ (simulta-
neously) and the clock is stable (stable clock is defined
as a signal cycling within timing constraints specified
for the clock pin), the SDRAM requires a 100µs delay
prior to issuing any command other than a COM-
MAND INHIBIT or NOP . Starting at some point during
this 100µs period and continuing at least through the
end of this period, Command Inhibit or NOP com-
mands should be applied.
one Command Inhibit or NOP command having been
applied, a PRECHARGE command should be applied.
All device banks must then be precharged, thereby
placing the device in the all device banks idle state.
be performed. After the AUTO refresh cycles are com-
plete, the SDRAM is ready for mode register program-
ming. Because the mode register will power up in an
unknown state, it should be loaded prior to applying
any operational command.
Mode Register Definition
mode of operation of the SDRAM. This definition
includes the selection of a burst length, a burst type, a
CAS latency, an operating mode and a write burst
mode, as shown in Mode Register Definition Diagram.
The mode register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
M3 specifies the type of burst (sequential or inter-
leaved), M4-M6 specify the CAS latency, M7 and M8
specify the operating mode, M9 specifies the write
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
Prior to normal operation, the SDRAM must be ini-
SDRAMs must be powered up and initialized in a
Once the 100µs delay has been satisfied with at least
Once in the idle state, two AUTO refresh cycles must
The mode register is used to define the specific
Mode register bits M0-M2 specify the burst length,
covering
device
initialization,
register
168-PIN REGISTERED SDRAM DIMM
7
128MB, 256MB, 512MB (x72, ECC)
burst mode, and M10 and M11 are reserved for future
use. For the 512MB module, address A12 (M12) is
undefined but should be driven LOW during loading of
the mode register.
banks are idle, and the controller must wait the speci-
fied time before initiating the subsequent operation.
Violating either of these requirements will result in
unspecified operation.
M12, M11, M10 = “0, 0, 0”
512MB Module
128MB and 256MB Modules
to ensure compatibility
with future devices.
to ensure compatibility
*Should program
The mode register must be loaded when all device
with future devices.
Figure 4: Mode Register Definition
M11, M10 = “0, 0”
*Should program
Reserved*
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Reserved* WB
12
11
A11
A12
Reserved*
10
A10
11
A11
9
10
A9
A10
Op Mode
WB
M9
0
1
8
9
A8
A9
Op Mode
7
8
A7
A8
CAS Latency
6
7
Diagram
A7
A6
Programmed Burst Length
M8
0
Single Location Access
CAS Latency
-
6
5
Write Burst Mode
A6
A5
5
4
M7
A5
0
-
A4
BT
4
A4
3
A3
M3
BT
M6-M0
Defined
0
1
3
Burst Length
A3
2
-
M2
M6
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
Burst Length
2
A2
M1
M5
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
A1
M0
M4
1
Operating Mode
Standard Operation
All other states reserved
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
A1
0
©2003, Micron Technology Inc.
A0
0
A0
Reserved
Reserved
Reserved
Full Page
M3 = 0
Mode Register (Mx)
Interleaved
Burst Type
Sequential
1
2
4
8
Address Bus
Mode Register (Mx)
Address Bus
Burst Length
CAS Latency
Reserved
Reserved
Reserved
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
M3 = 1
1
2
4
8