MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 6

• Manufacturer Part Number: MT18LSDT6472G-13ED2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 4831838208
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

General Description
MT18LSDT6472G are high-speed CMOS, dynamic ran-
dom-access, 128MB, 256MB, and 512MB memory
modules organized in a x72 (ECC) configuration.
These modules use internally configured quad-bank
SDRAM devices, with a synchronous interface (all sig-
nals are registered on the positive edge of clock signal
CK0).
burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select the device bank, A0-A11
select the device row for the 128MB and 256MB mod-
ules; A0-A12 select the device row for the 512MB mod-
ule). The address bits registered coincident with the
READ or WRITE command are used to select the start-
ing device column location for the burst access.
write burst lengths of 1, 2, 4, or 8 locations, or full page,
with a burst terminate option. An auto precharge
function may be enabled to provide a self-timed
device row precharge that is initiated at the end of the
burst sequence.
ture. Precharging one device bank while accessing one
of the other three device banks will hide the PRE-
CHARGE cycles and provide seamless, high-speed,
random-access operation.
power memory systems. An auto refresh mode is pro-
vided, along with a power-saving, power-down mode.
All inputs and outputs are LVTTL-compatible.
DRAM operating performance, including the ability to
synchronously burst data at a high data rate with auto-
matic device column-address generation, the ability to
interleave between device banks in order to hide pre-
charge time, and the capability to randomly change
device column addresses on each clock cycle during a
burst access. For more information regarding SDRAM
operation, refer to the 64Mb, 128Mb, and 256Mb
SDRAM data sheets.
PLL and Register Operation
mode (REGE pin HIGH), where the control/address
input signals are latched in the register on one rising
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
The
Read and write accesses to the SDRAM modules are
These modules provide for programmable read or
These modules use an internal pipelined architec-
These modules are designed to operate in 3.3V, low-
SDRAM modules offer substantial advances in
These modules can be operated in either registered
MT18LSDT1672G,
MT18LSDT3272G,
and
168-PIN REGISTERED SDRAM DIMM
6
128MB, 256MB, 512MB (x72, ECC)
clock edge and sent to the SDRAM devices on the fol-
lowing rising clock edge (data access is delayed by one
clock), or in buffered mode (REGE pin LOW) where the
input signals pass through the register/buffer to the
SDRAM devices on the same clock. A phase-lock loop
(PLL) on the modules is used to redrive the clock sig-
nals to the SDRAM devices to minimize system clock
loading (CK0 is connected to the PLL, and CK1, CK2,
and CK3 are terminated).
Serial Presence-Detect Operation
(SPD).
2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be pro-
grammed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hard-
ware write protect.
SDRAM Component Description
memory devices used for these modules are quad-
bank DRAMs, that operate at 3.3V and include a syn-
chronous interface (all signals are registered on the
positive edge of the clock signal, CK). The four banks
of a x4, 64Mb device are each configured as 4,096 bit-
rows, by 1,024 bit-columns, by 4 input/output bits. The
four banks of a x4, 128Mb device are each configured
as 4,096 bit-rows, by 2,048 bit-columns, by 4 input/
output bits. The four banks of a x4, 256MB device are
configured as 8,192 bit-rows, by 2,048 bit columns, by 4
input/output bits.
Module Functional Description
ented; accesses start at a selected location and con-
tinue for a programmed number of locations in a
programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed BA0 and BA1 select the device bank, A0-A11
(for 128MB and 256MB module), or A0-A12 (for 512MB
These modules incorporate serial presence-detect
In general, the 64Mb, 128Mb, and 256Mb SDRAM
Read and write accesses to the SDRAM are burst ori-
Micron Technology, Inc., reserves the right to change products or specifications without notice.
The SPD function is implemented using a
©2003, Micron Technology Inc.
2
C bus