MT18LSDT6472G-13ED2 Micron Technology Inc, MT18LSDT6472G-13ED2 Datasheet - Page 8

• Manufacturer Part Number: MT18LSDT6472G-13ED2
• Description: MODULE SDRAM 512MB 168DIMM
• Manufacturer: Micron Technology Inc

Specifications of MT18LSDT6472G-13ED2

• Memory Type: SDRAM
• Memory Size: 512MB
• Speed: 133MHz
• Package / Case: 168-DIMM
• Main Category: DRAM Module
• Sub-category: SDRAM
• Module Type: 168RDIMM
• Device Core Size: 72b
• Organization: 64Mx72
• Total Density: 4831838208
• Chip Density: 256Mb
• Access Time (max): 5.4ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Current: 2.43A
• Number Of Elements: 18
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 55C
• Operating Temperature Classification: Commercial
• Pin Count: 168
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Burst Length
ented, with the burst length being programmable, as
shown in Mode Register Definition Diagram. The burst
length determines the maximum number of column
locations that can be accessed for a given READ or
WRITE command. Burst lengths of 1, 2, 4, or 8 loca-
tions are available for both the sequential and the
interleaved burst types, and a full-page burst is avail-
able for the sequential type. The full-page burst is used
in conjunction with the BURST TERMINATE com-
mand to generate arbitrary burst lengths.
operation or incompatibility with future versions may
result.
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached, as shown in the Burst
Definition Table. The block is uniquely selected by A1-
A9 (64MB) or A1-A9, A11 (128MB/256MB) when the
burst length is set to two; A2-A9 or A2-A9, A11 when
the burst length is set to four; and by A3-A9 or A3-A9,
A11 when the burst length is set to eight. The remain-
ing (least significant) address bit(s) is (are) used to
select the starting location within the block. Full-page
bursts wrap within the page if the boundary is reached,
as shown in the Burst Definition Table.
Burst Type
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
mined by the burst length, the burst type and the start-
ing column address, as shown in the Burst Definition
Table.
CAS Latency
between the registration of a READ command and the
availability of the first piece of output data. The latency
can be set to two or three clocks.
16,32,Meg x 64 DDR SDRAM DIMMs (Footer Desc variable)
SD18C16_32_64x72G_B.fm - Rev. B 1/03 EN
Read and write accesses to the SDRAM are burst ori-
Reserved states should not be used, as unknown
When a READ or WRITE command is issued, a block
Accesses within a given burst may be programmed
The ordering of accesses within a burst is deter-
The CAS latency is the delay, in clock cycles,
168-PIN REGISTERED SDRAM DIMM
8
128MB, 256MB, 512MB (x72, ECC)
Table 7:
NOTE:
1. For full-page accesses: y = 1,024 (128MB); y= 2,048
2. For a burst length of two, A1–A9 (128MB) or A1–
3. For a burst length of four, A2–A9 or A2–A9/A11
4. For a burst length of eight, A3–A9 or A3–A9/A11
5. For a full-page burst, the full row is selected and
6. Whenever a boundary of the block is reached
7. For a burst length of one, A0–A9 or A0–A9/A11
LENGTH
BURST
Page
M
(256MB and512MB).
A9/A11(256MB and512MB) select the block of two
burst; A0 selects the starting column within the
block.
select the block of four burst; A0–A1 select the
starting column within the block.
select the block of eight burst; A0–A2 select the
starting column within the block.
A0–A9 or A0–A9/A11 select the starting column.
within a given sequence above, the following
access wraps within the block.
select the unique column to be accessed, and Mode
Register bit M3 is ignored.
Full
(y)
2
4
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
n = A0-A9, or
n =A0-A9/A11
(location 0-y)
A2 A1 A0
STARTING
ADDRESS
0
0
0
0
1
1
1
1
COLUMN
Burst Definition Table
A1 A0
0
0
1
1
0
0
1
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Cn, Cn+1, Cn+2,
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
SEQUENTIAL
Cn+3, Cn+4...,
...Cn-1, Cn...
TYPE =
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
ORDER OF ACCESSES
0-1
1-0
WITHIN A BURST
©2003, Micron Technology Inc.
INTERLEAVED
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Notsupported
TYPE =
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1
1-0