MT18VDVF12872DG-40BF1 Micron Technology Inc, MT18VDVF12872DG-40BF1 Datasheet - Page 20

• Manufacturer Part Number: MT18VDVF12872DG-40BF1
• Description: MODULE DDR 1GB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872DG-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184VLPRDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 13:
Table 14:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
AC Characteristics
Parameter
Access window of DQs from CK/CK#
CK high-level width
CK low-level width
Clock cycle time
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew, DQS to last DQ valid, per group,
per access
Write command to first DQS latching transition
DQS falling edge to CK rising - setup time
DQS falling edge from CK rising - hold time
Half clock period
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (fast slew
rate)
Address and control input setup time (fast slew
rate)
Address and control input hold time (slow slew
rate)
Address and control input setup time (slow slew
rate)
Address and Control input pulse width (for each
input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid,
per access
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
Parameter
Input/Output Capacitance: DQ, DQS, DM
Input Capacitance: Command and Address, S#, CKE
Input Capacitance: CK, CK#
Capacitance (512MB only)
Note: 11; notes appear on pages 22–26
Electrical Characteristics and Recommended AC Operating Conditions
DDR SDRAM components only
Notes: 1–5, 12–15, 29, 48; notes appear on pages 22–26; 0°C ≤ T
CL = 2.5
CL = 2
t
Symbol
t
CK (2.5)
t
t
DQSCK
t
t
t
t
t
CK (2)
DQSQ
DQSH
t
DIPW
DQSL
DQSS
t
t
t
t
t
MRD
t
t
QHS
t
t
DSH
t
t
t
t
RAP
t
t
DSS
t
t
IPW
RAS
t
QH
AC
CH
DH
DS
HP
HZ
IH
IH
CL
IS
IS
LZ
F
S
F
S
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
20
-0.60
-0.70
t
t
0.45
0.45
0.45
0.45
1.75
0.35
0.35
0.75
0.75
0.75
0.80
0.80
2.20
Min
-0.7
QHS
HP -
7.5
0.2
0.2
12
42
15
6
t
CH,
-335
120,000
+0.60
t
+0.70
Max
+0.7
0.55
0.55
0.35
1.25
CL
0.50
13
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
7.5/10
-0.75
-0.75
-0.75
t
t
A
0.45
0.45
1.75
0.35
0.35
0.75
0.90
0.90
2.20
Min
HP -
QHS
7.5
0.5
0.5
0.2
0.2
15
40
15
Symbol
1
1
≤ +70°C; V
t
CH,
C
C
C
-262
I0
I1
I2
120,000
+0.75
+0.75
t
+0.75
Max
0.55
0.55
1.25
0.75
CL
0.5
13
13
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
DD
Electrical Specifications
7.5/10
= V
-0.75
-0.75
-0.75
t
t
0.45
0.45
1.75
0.35
0.35
0.75
2.20
Min
QHS
HP -
7.5
0.5
0.5
0.2
0.2
.90
.90
15
40
20
-26A/-265
1
1
t
DD
CH,
Min
2.5
Q = +2.5V ±0.2V
8
–
120,000
+0.75
+0.75
t
+0.75
Max
0.55
0.55
1.25
0.75
CL
0.5
13
13
Max
3.5
10
4
Units
t
t
t
t
t
t
t
ns
CK
CK
ns
ns
ns
ns
ns
ns
CK
CK
ns
CK
CK
CK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
pF
Notes
40, 45
40, 45
23, 27
23, 27
22, 23
16, 37
16, 37
22, 23
31, 48
pF
pF
26
26
27
30
12
12
12
12