MT18VDVF12872DG-40BF1 Micron Technology Inc, MT18VDVF12872DG-40BF1 Datasheet - Page 27

• Manufacturer Part Number: MT18VDVF12872DG-40BF1
• Description: MODULE DDR 1GB 184-DIMM VLP
• Manufacturer: Micron Technology Inc

Specifications of MT18VDVF12872DG-40BF1

• Memory Type: DDR SDRAM
• Memory Size: 1GB
• Speed: 400MT/s
• Package / Case: 184-DIMM
• Main Category: DRAM Module
• Sub-category: DDR SDRAM
• Module Type: 184VLPRDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 512Mb
• Maximum Clock Rate: 400MHz
• Operating Supply Voltage (typ): 2.6V
• Operating Current: 1.8A
• Number Of Elements: 18
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.5V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 184
• Mounting: Socket
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Initialization
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
10. Wait at least
11. Using the LMR command, program the mode register to set operating parameters
12. Wait at least
13. Issue a PRECHARGE ALL command.
14. Wait at least
15. Issue an AUTO REFRESH command (this may be moved prior to step 13).
16. Wait at least
17. Issue an AUTO REFRESH command (this may be moved prior to step 13).
18. Wait at least
19. Although not required by the Micron device, JEDEC requires a LMR command to clear
20. Wait at least
1. Simultaneously apply power to V
2. Apply V
3. Assert and hold CKE at a LVCMOS logic LOW.
4. Provide stable clock signals.
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or DESELECT command. At this point
7. Perform a PRECHARGE ALL command.
8. Wait at least
9. Using the LMR command program the extended mode register (E0 = 0 to enable the
To ensure device operation the DRAM must be initialized as described below:
At this point the module is ready for any valid command. Please note that 200 clock
cycles must pass between step 11 (DLL Reset) and any READ command.
the CKE input changes from a LVCMOS input to a SSTL2 input only, and will remain a
SSTL_2 input unless a power cycle occurs.
DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set
to 0; where n = most significant bit).
and to reset the DLL. At least 200 clock cycles are required between a DLL reset and
any READ command.
the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters
should be utilized as in step 11.
REF
and then V
t
t
t
t
t
t
t
RP time, during which NOP or DESELECT commands must be given.
MRD time; only NOP or DESELECT commands are allowed.
MRD time; only NOP or DESELECT commands are allowed.
RP time; only NOP or DESELECT commands are allowed.
RFC time; only NOP or DESELECT commands are allowed.
RFC time: only NOP or DESELECT commands are allowed.
MRD time; only NOP or DESELECT commands are allowed.
TT
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
power.
27
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and V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
Q.
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
Initialization