MT18VDVF12872DG-40BF1 Micron Technology Inc, MT18VDVF12872DG-40BF1 Datasheet - Page 29
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MT18VDVF12872DG-40BF1
Manufacturer Part Number
MT18VDVF12872DG-40BF1
Description
MODULE DDR 1GB 184-DIMM VLP
Manufacturer
Micron Technology Inc
Specifications of MT18VDVF12872DG-40BF1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184VLPRDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Operating Current
1.8A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Register and PLL Specifications
Table 15:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
Register
by JESD82-3
(bit pattern
or JESD82-4
SSTL
Register Timing Requirements and Switching Characteristics
Note 1
Symbol
f
t
clock
t
t
t
inact
t
t
t
PHL
act
pd
su
w
h
Notes: 1. The timing and switching specifications for the register listed above are critical for proper
Setup Time, Slow Slew Rate
Differential Inputs Inactive
Setup Time, Fast Slew Rate
Hold Time, Slow Slew Rate
Hold Time, Fast Slew Rate
Differential Inputs Active
2. Data inputs must be low a minimum time of t
3. Data and clock inputs must be held at valid levels (not floating) a minimum time of t
4. For data signal input slew rate ≥ 1 V/ns.
5. For data signal input slew rate ≥ 0.5 V/ns and
6. CK, CK# signals input slew rate ≥ 1 V/ns.
Clock to Output Time
Reset to Output Time
Clock Frequency
operation of DDR SDRAM registered DIMMs. These are meant to be a subset of the param-
eters for the specific device used on the module. Detailed information for this register is
available in JEDEC Standard JESD82.
MAX, after RESET# is taken LOW.
Pulse Duration
Paramerter
Time
Time
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
30pF to GND and
CK, CK# HIGH or
HIGH, CK# LOW
HIGH, CK# LOW
Data Before CK
Data After CK
29
Condition
50Ω to V
LOW
TT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
<
act
V
Register and PLL Specifications
0°C ≤ T
1 V/ns.
DD
max, after RESET# is taken HIGH.
Min
0.75
0.75
1.1
2.5
0.9
0.9
-
-
-
-
= 2.5V ± 0.2V
A
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
≤ +70°C
Max
200
2.8
22
22
5
-
-
-
-
-
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4, 6
5, 6
4, 6
5, 6
2
3
inact