MT18VDVF12872DG-40BF1 Micron Technology Inc, MT18VDVF12872DG-40BF1 Datasheet - Page 35
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MT18VDVF12872DG-40BF1
Manufacturer Part Number
MT18VDVF12872DG-40BF1
Description
MODULE DDR 1GB 184-DIMM VLP
Manufacturer
Micron Technology Inc
Specifications of MT18VDVF12872DG-40BF1
Memory Type
DDR SDRAM
Memory Size
1GB
Speed
400MT/s
Package / Case
184-DIMM
Main Category
DRAM Module
Sub-category
DDR SDRAM
Module Type
184VLPRDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
512Mb
Maximum Clock Rate
400MHz
Operating Supply Voltage (typ)
2.6V
Operating Current
1.8A
Number Of Elements
18
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.5V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
184
Mounting
Socket
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Table 19:
Table 20:
PDF: 09005aef81c73825/Source: 09005aef81c73837
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
Parameter/Condition
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs
Input Low Voltage: Logic 0; All inputs
Output Low Voltage: I
Input Leakage Current: V
Output Leakage Current: V
Standby Current: SCL = SDA = V
Power Supply Current, READ: SCL clock frequency = 100 KHz
Powr Supply Current, WRITE: SCL clock frequency = 100 KHz
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to V
Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to V
Notes: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1
OUT
IN
= 3mA
OUT
= GND to V
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
= GND to V
DD
and the falling or rising edge of SDA.
write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE
cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resis-
tor, and the EEPROM does not respond to its slave address.
- 0.3V; All other inputs = V
DD
SS
SS
DD
; V
; V
DDSPD
DDSPD
= +2.3V to +3.6V
= +2.3V to +3.6V
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
35
DD
or V
SS
t
WRC) is the time from a valid stop condition of a
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Symbol
t
Symbol
t
t
t
t
V
HD:DAT
HD:STA
SU:DAT
SU:STO
SU:STA
t
t
t
t
HIGH
DDSPD
I
LOW
f
WRC
t
t
V
I
V
BUF
I
CC
V
I
SCL
CC
AA
DH
I
t
LO
t
SB
t
OL
LI
IH
F
R
IL
I
W
R
V
DDSPD X
Min
0.10
0.05
-0.6
2.3
1.6
0.4
Min
200
100
2
0.2
1.3
0.6
0.6
1.3
0.6
0.6
–
©2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
0
Serial Presence-Detect
0.7
Max
300
400
0.9
0.3
50
10
V
V
DDSPD
DDSPD
Max
3.6
0.4
Units
3
3
4
1
3
KHz
ms
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
ns
µs
µs
+ 0.5
x 0.3
Notes
Units
mA
mA
µA
µA
µA
1
2
2
3
4
V
V
V
V