TMP86C993XB Toshiba, TMP86C993XB Datasheet - Page 127

• Manufacturer Part Number: TMP86C993XB
• Description: EMULATION CHIP FOR TMP86F SSOP
• Manufacturer: Toshiba

Specifications of TMP86C993XB

• Accessory Type: Adapter
• For Use With/related Products: TMP86F SSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz)
11.3.8
to enter the 16-bit PPG mode.
the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched
to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to
the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value
is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time.
generated. Upon reset, the timer F/F4 is cleared to 0.
→ PWREG4) (Programming only the upper or lower byte should not be attempted.)
frequency to be supplied is fc/2
SLEEP1/2 mode.
Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and
Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To
Note 3: i = 3, 4
This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable
The counter counts up using the internal clock or external clock. When a match between the up-counter and
Since the initial value can be set to the timer F/F4 by TC4CR<TFF4>, positive and negative pulses can be
(The logic level output from the PPG4 pin is the opposite to the timer F/F4.)
Set the lower byte and upper byte in this order to program the timer register. (TTREG3 → TTREG4, PWREG3
For PPG output, set the output latch of the I/O port to 1.
Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum
16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4)
TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and
TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are
changed while the timer is running, an expected operation may not be obtained.
change the output status, program TC4CR<TFF4> after the timer is stopped. Do not change TC4CR<TFF4> upon
stopping of the timer.
Example: Fixing the PPG4 pin to the high level when the TimerCounter is stopped
CLR (TC4CR).3 ; Stops the timer
CLR (TC4CR).7 ; Sets the PPG4 pin to the high level
LDW
LDW
LD
LD
LD
Setting ports
(PWREG3), 07D0H
(TTREG3), 8002H
(TC3CR), 33H
(TC4CR), 057H
(TC4CR), 05FH
4
Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/2
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; Sets the pulse width.
; Sets the cycle period.
; Sets the operating clock to fc/2
; (lower byte).
; Sets TFF4 to the initial value 0, and 16-bit
; PPG mode (upper byte).
; Starts the timer.
3
, and16-bit PPG mode
4
to in the SLOW1/2 or
TMP86FH92DMG