PBMCUSLK Freescale Semiconductor, PBMCUSLK Datasheet - Page 27

• Manufacturer Part Number: PBMCUSLK
• Description: PROJECT BOARD FOR MCU
• Manufacturer: Freescale Semiconductor

Specifications of PBMCUSLK

• Module/board Type: Student Learning Kit
• Silicon Manufacturer: Freescale
• Core Architecture: HCS08, S12
• Core Sub-architecture: HCS08, S12
• Silicon Core Number: MC9S08, MC9S12
• Silicon Family Name: S08QG, S12D
• Rohs Compliant: Yes
• For Use With/related Products: HC(S)12(X), HC(S)08, DSP, and ColdFire modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Signal Breakout
The following chart shows the signal breakout for the NI-ELVIS signals. These connectors are
arranged from left to right above the breadboard. All signals are grouped by function and
arranged to provide convenient access to the breadboard. Each signal group is labeled to ease
signal identification and location. To ease prototyping, each signal is routed to two socket
locations. This allows the user to easily route each to signal to multiple locations if desired.
The table below details the NI-ELVS signal breakout connectors.
Figure 18: NI-ELVIS Signal Breakout – J2, J3, J4
Freescale Semiconductor
11 12 3-WIRE
13 14 CURRENT HI
15 16 CURRENT LO
17 18 VOLTAGE HI
19 20 VOLTAGE LO
21 22 AM IN
23 24 FM IN
25 26 FUNC OUT
27 28 SYNC OUT
29 30 CH A+
31 32 CH A-
33 34 CH B+
35 36 CH B-
37 38 TRIGGER
39 40 AISENSE
41 42 AIGND
43 44 ACH0+
45 46 ACH0-
47 48 ACH1+
49 50 ACH1-
51 52 ACH2+
53 54 ACH2-
55 56 ACH3+
57 58 ACH3-
59 60 ACH4+
9
1
3
5
7
J2
10 DAC 1
2 SUPPLY+
4 GND
6 SUPPLY-
8 DAC0
11 12 CTR0_GATE
13 14 CTR0_OUT
15 16 CTR1_SOURCE
17 18 CTR1_GATE
19 20 CTR1_OUT
21 22 5 V
23 24 5 V
25 26 RESERVED
27 28 SCAN CLK
29 30 PFI 1
31 32 PFI 2
33 34 PFI 5
35 36 PFI 6
37 38 PFI 7
39 40 3.3 V
1
3
5
7
9
J3
10 CTR0_SOURCE
2 ACH4-
4 ACH5+
6 ACH5-
8 FREQ_OUT
11 12 ADDRESS 0
13 14 ADDRESS 1
15 16 ADDRESS 2
17 18 ADDRESS 3
19 20 VDD
21 22 VDD
23 24 DO 0
25 26 DO 1
27 28 DO 2
29 30 DO 3
31 32 DO 4
33 34 DO 5
35 36 DO 6
37 38 DO 7
39 40 GND
41 42 DI 0
43 44 DI 1
45 46 DI 2
47 48 DI 3
49 50 DI 4
51 52 DI 5
53 54 DI 6
55 56 DI 7
57 58 +15 V
59 60 -15 V
1
3
5
7
9 10 GLB_RESET*
J4
2 3.3 V
4 WR_ENABLE*
6 RD_ENABLE*
8 LATCH*
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