KSZ8851-16MLL-EVAL Micrel Inc, KSZ8851-16MLL-EVAL Datasheet - Page 52

• Manufacturer Part Number: KSZ8851-16MLL-EVAL
• Description: BOARD EVALUATION KSZ8851-16MLL
• Manufacturer: Micrel Inc
• Series: LinkMD®r

Specifications of KSZ8851-16MLL-EVAL

• Main Purpose: Interface, Ethernet Controller (PHY and MAC)
• Embedded: No
• Utilized Ic / Part: KSZ8851-16MLL
• Primary Attributes: 1 Port, 100BASE-TX/10BASE-T
• Secondary Attributes: 8/16-Bit Interface, LinkMD Cable Diagnostics
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 576-3292

TXQ Command Register (0x80 – 0x81): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
RXQ Command Register (0x82 – 0x83): RXQCR
This register is programmed by the Host CPU to issue DMA read or write command to the RXQ and TXQ. This register
also is used to control all RX thresholds enable and status.
August 2009
Micrel, Inc.
Bit
15-3
2
1
0
Bit
15-13
12
11
10
9
8
7
6
-
0x0
0x0
0x0
-
-
-
-
0x0
-
0x0
0x0
Default Value
Default Value
R/W
RW
RW
RW
RW
R/W
RW
RO
RO
RO
RW
RW
RW
RW
Description
Reserved
AETFE Auto-Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will enable current all TX frames
prepared in the TX buffer are queued to transmit automatically.
The bit 0 METFE has to be set 0 when this bit is set to 1 in this register.
TXQMAM TXQ Memory Available Monitor
When this bit is written as 1, the KSZ8851-16MLL will generate interrupt (bit 6 in ISR
register) to CPU when TXQ memory is available based upon the total amount of TXQ
space requested by CPU at TXNTFSR (0x9E) register.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before set to 1 again.
METFE Manual Enqueue TXQ Frame Enable
When this bit is written as 1, the KSZ8851-16MLL will enable current TX frame prepared
in the TX buffer is queued for transmit, this is only transmit one frame at a time.
Note: This bit is self-clearing after the frame is finished transmitting. The software should
wait for the bit to be cleared before setting up another new TX frame.
Description
Reserved.
RXDTTS RX Duration Timer Threshold Status
When this bit is set, it indicates that RX interrupt is due to the time start at first received
frame in RXQ buffer exceeds the threshold set in RX Duration Timer Threshold Register
(0x8C, RXDTT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXDBCTS RX Data Byte Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received bytes in
RXQ buffer exceeds the threshold set in RX Data Byte Count Threshold Register (0x8E,
RXDBCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXFCTS RX Frame Count Threshold Status
When this bit is set, it indicates that RX interrupt is due to the number of received frames
in RXQ buffer exceeds the threshold set in RX Frame Count Threshold Register (0x9C,
RXFCT).
This bit will be updated when write 1 to bit 13 in ISR register.
RXIPHTOE RX IP Header Two-Byte Offset Enable
When this bit is written as 1, the KSZ8851-16MLL will enable to add two bytes before
frame header in order for IP header inside the frame contents to be aligned with double
word boundary to speed up software operation.
Reserved.
RXDTTE RX Duration Timer Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR)
when the time start at first received frame in RXQ buffer exceeds the threshold set in RX
Duration Timer Threshold Register (0x8C, RXDTT).
RXDBCTE RX Data Byte Count Threshold Enable
When this bit is written as 1, the KSZ8851-16MLL will enable RX interrupt (bit 13 in ISR)
52
KSZ8851-16MLL/MLLI
M9999-083109-2.0