STEVAL-ISF002V1 STMicroelectronics, STEVAL-ISF002V1 Datasheet - Page 30

BOARD EVALUATION

STEVAL-ISF002V1

Manufacturer Part Number
STEVAL-ISF002V1
Description
BOARD EVALUATION
Manufacturer
STMicroelectronics
Datasheets

Specifications of STEVAL-ISF002V1

Main Purpose
*
Embedded
*
Utilized Ic / Part
*
Primary Attributes
*
Secondary Attributes
*
Product
Power Management Modules
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-10422

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Digital PFC firmware
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6.1
30/62
Digital PFC firmware
This chapter describes and explains how to implement the digital PFC software.
Firmware architecture
The execution of the PFC firmware is based on the implementation of a state machine. It is
basically made up of four states.
PFC_WAITING: after initialization, the system waits for the AC mains insertion,
triggered by a falling edge of the zero-crossing detector shown in
time, the new state assumed is PFC_STARTING.
PFC_STARTING: the mains frequency is measured and if it is outside the range of
45 ÷ 66 Hz, the new state becomes PFC STOPPED. If the mains frequency is within
this range, the relay against in-rush current is closed and protections are enabled. To
avoid current peaks, the VDC setpoint for the voltage PI is not immediately fixed to the
final target. The actual VDC reference is gradually increased to reach the final target
voltage of 415 V. The growth of this reference is shown in
by the PFC_ROUTINE function (part of the "PFC.c" file) every 25 µs. This method of
gradually incrementing to reach the target output voltage reference is called soft-start .
Doc ID 16854 Rev 1
Figure 26
Figure 22
and it is managed
. After this
UM0877

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