EVB9303 SMSC, EVB9303 Datasheet - Page 206

• Manufacturer Part Number: EVB9303
• Description: EVALUATION BOARD FOR LAN9303
• Manufacturer: SMSC

Specifications of EVB9303

• Main Purpose: Interface, Ethernet
• Embedded: No
• Utilized Ic / Part: LAN9303
• Primary Attributes: 3 Ports, 100BASE-TX/10BASE-T, Managed
• Secondary Attributes: Full Duplex and HP Auto-MDIX Support, 10BASE-T and 100BASE-TX
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 638-1095

Revision 1.4 (07-07-10)
13.3.2.9
MODE[2:0]
BITS
15:8
7:5
4:0
000
001
010
011
100
101
110
111
RESERVED
PHY Mode (MODE[2:0])
This field reflects the default PHY mode of operation. Refer to
for a definition of each mode.
PHY Address (PHYADD)
The PHY Address field determines the MMI address to which the PHY will
respond and is also used for initialization of the cipher (scrambler) key. Each
PHY must have a unique address. Refer to
Addressing," on page 88
Note:
Port x PHY Special Modes Register (PHY_SPECIAL_MODES_x)
This read/write register is used to control the special modes of the Port x PHY.
Note: This register is re-written by the EEPROM Loader following the release of reset or a RELOAD
Note 13.63 Register bits designated as NASR are reset when the Port x PHY Reset is generated via
Note 13.64 The default value of this field is determined by a combination of the configuration straps
Note 13.65 The default value of this field is determined by the
10BASE-T Half Duplex. Auto-negotiation disabled.
10BASE-T Full Duplex. Auto-negotiation disabled.
100BASE-TX Half Duplex. Auto-negotiation disabled. CRS is active during Transmit & Receive.
100BASE-TX Full Duplex. Auto-negotiation disabled. CRS is active during Receive.
RESERVED
RESERVED
Power Down mode.
All capable. Auto-negotiation enabled.
No check is performed to ensure this address is unique from the
other PHY addresses (Port 1 PHY, Port 2 PHY, and Virtual PHY).
command. Refer to
Index (decimal): 18
the
t h e
(PHY_BASIC_CONTROL_x)
autoneg_strap_x, speed_strap_x, and duplex_strap_x. If the autoneg_strap_x is 1, then
the default MODE[2:0] value is 111b. Else, the default value of this field is determined by
the remaining straps. MODE[2]=0,
speed_strap_2
duplex_strap_2
assertion of a chip-level reset as described in
page
Refer to
Reset Control Register
R e s e t ( P H Y _ R S T )
45. Refer to
Section 7.1.1, "PHY Addressing," on page 88
for additional information.
Table 13.11 MODE[2:0] Definitions
DESCRIPTION
Section 8.4, "EEPROM Loader," on page 113
for Port 2 PHY). Configuration strap values are latched upon the de-
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
for Port 2 PHY), and
Section 4.2.4, "Configuration Straps," on page 45
DATASHEET
(RESET_CTL). The NASR designation is only applicable when
MODE DEFINITIONS
is set.
Section 7.1.1, "PHY
b i t o f t h e
206
Size:
MODE[1]=(speed_strap_1
MODE[0]=(duplex_strap_1
P o r t x P H Y B a s i c C o n t r o l R e g i s t e r
Section 4.2.4, "Configuration Straps," on
Table 13.11
phy_addr_sel_strap
16 bits
for additional information.
for more information.
Note 13.63
Note 13.63
NASR
NASR
TYPE
R/W
R/W
SMSC LAN9303/LAN9303i
RO
for strap definitions.
configuration strap.
for Port 1 PHY,
for Port 1 PHY,
DEFAULT
Note 13.64
Note 13.65
Datasheet
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