WAVEVSN BRD 4.4 National Semiconductor, WAVEVSN BRD 4.4 Datasheet - Page 7

• Manufacturer Part Number: WAVEVSN BRD 4.4
• Description: BOARD INTERFACE DIGITAL HI SPD
• Manufacturer: National Semiconductor
• Series: WaveVisionr

Specifications of WAVEVSN BRD 4.4

• Main Purpose: Interface, Data Capture
• Embedded: Yes, ASIC
• Primary Attributes: ADC & DAC Evaluation
• Secondary Attributes: Graphical User Interface, USB Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Utilized Ic / Part: -

2.3 Automatic Device Detection & Configuration
The WaveVision4 system provides automatic hardware detection and configuration for the device under
test. The FPGA is re-programmed on the fly by the host PC when the WaveVision4 Data Capture Board
is turned on, or whenever the ADC or DAC evaluation boards are exchanged.
Normally, the configuration process is totally transparent to the user, and requires no intervention.
However, this process can be overridden if required. Refer to the device evaluation board manual for
more information.
Important Note: Many of our evaluation boards do require jumper configurations to select channels,
voltages, or other options. Please consult the manual that came with the evaluation board for specific
information.
2.4 Modes of Operation & LED Indicators
ADC Evaluation Boards
Data acquisition by the WaveVision4 System is divided into three phases:
LEDs on the WaveVision4 Data Capture Board indicate each of these phases. During the frequency
counting phase, LED2 “UPLOAD” will be lit momentarily. The frequency count should take about a tenth
of a second to complete.
During the collection phase, LED3 “SAMPLE” will be illuminated. The collection should generally take less
than a quarter second, but may be longer for low-speed devices.
During the upload phase, LED2 “UPLOAD” will be illuminated. The upload takes approximately 10
seconds to transfer the entire SRAM contents (2
adequate.
When no action is being taken by the WaveVision4 System, LED 4 “IDLE” will be illuminated. This LED
also indicates that the FPGA has been programmed correctly. This LED should be “ON” before
attempting to start a data acquisition.
LED5 “ADC_CLOCK” is used to determine whether an ADC Evaluation Board clock is active. This LED
flashes to indicate that the FPGA is receiving a clock signal from the Evaluation board.
DAC Evaluation Boards
For the DAC evaluation boards, the phases are download waveform data/frequency and run. LED3
“SAMPLE” indicates the download is occurring. LED2 “UPLOAD” indicates that the DAC is running. LED4
and LED5 have equivalent functions as for the ADC evaluation boards.
1. Frequency Count: The clock frequency of the ADC or DAC under test is measured and sent
2. Sample: ADC Data Samples are clocked into the SRAM.
3. Upload: Sample data is transferred to the host PC.
back to the host PC.
17
samples). For many purposes, 2
7
15
samples are