DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 145
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DS26528DK
Manufacturer Part Number
DS26528DK
Description
KIT DESIGN FOR DS26528
Manufacturer
Maxim Integrated Products
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528DK
Main Purpose
Telecom, Framer and Line Interface Units (LIUs)
Utilized Ic / Part
G575DS26528
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: This register has an alternate definition for T1 mode. See
Bit 6: Receive HDB3 Enable (RHDB3).
Bit 5: Receive-Signaling Mode Select (RSIGM).
Bit 4: Receive G.802 Enable (RG802). See
Bit 3: Receive CRC-4 Enable (RCRC4).
Bit 2: Frame Resync Criteria (FRC).
Bit 1: Sync Enable (SYNCE).
Bit 0: Resynchronize (RESYNC). When toggled from low to high, a resynchronization of the receive-side framer is
initiated. Must be cleared and set again for a subsequent resync.
0 = HDB3 disabled
1 = HDB3 enabled (decoded per O.162)
0 = CAS signaling mode
1 = CCS signaling mode
0 = do not force RCHBLK high during bit 1 of time slot 26
1 = force RCHBLK high during bit 1 of time slot 26
0 = CRC-4 disabled
1 = CRC-4 enabled
0 = resync if FAS received in error three consecutive times
1 = resync if FAS or bit 2 of non-FAS is received in error three consecutive times
0 = auto resync enabled
1 = auto resync disabled
—
7
0
RCR1 (E1 Mode)
Receive Control Register 1
081h + (200h x n): where n = 0 to 7, for Ports 1 to 8
RHDB3
6
0
RSIGM
5
0
Figure 10-23
RCR1
145 of 276
RG802
4
0
.
for details.
RCRC4
3
0
DS26528 Octal T1/E1/J1 Transceiver
FRC
2
0
SYNCE
1
0
RESYNC
0
0
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