DS26528DK Maxim Integrated Products, DS26528DK Datasheet - Page 63

• Manufacturer Part Number: DS26528DK
• Description: KIT DESIGN FOR DS26528
• Manufacturer: Maxim Integrated Products

Specifications of DS26528DK

• Main Purpose: Telecom, Framer and Line Interface Units (LIUs)
• Utilized Ic / Part: G575DS26528
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Secondary Attributes: -
• Embedded: -
• Primary Attributes: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.9.9.4 E-Bit Counter (EBCR)
This counter is only available in E1 mode. E-Bit Count Register 1 (E1EBCR1) is the most significant word and E-Bit
Count Register 2 (E1EBCR2) is the least significant word of a 16-bit counter that records far-end block errors
(FEBE) as reported in the first bit of frames 13 and 15 on E1 lines running with CRC-4 multiframe. These count
registers increment once each time the received E-bit is set to 0. Since the maximum E-bit count in a one-second
period is 1000, this counter cannot saturate. The counter is disabled during loss of sync at either the FAS or CRC-4
level; it continues to count if loss of multiframe sync occurs at the CAS level.
8.9.10 DS0 Monitoring Function
The DS26528 can monitor one DS0 (64kbps) channel in the transmit direction and one DS0 channel in the receive
direction at the same time.
Table 8-29. Registers Related to DS0 Monitoring
Transmit DS0 Channel Monitor Select
(TDS0SEL)
Transmit DS0 Monitor Register
(TDS0M)
Receive Channel Monitor Select Register
(RDS0SEL)
Receive DS0 Monitor Register
(RDS0M)
Note: The addresses shown are for Framer 1. Addresses for Framers 2 to 8 can be calculated using the following: Framer n = (Framer 1
address + (n - 1) x 200h); where n = 2 to 8 for Framers 2 to 8.
In the transmit direction, the user determines which channel is to be monitored by properly setting the TCM[4:0] bits
in the
set. The DS0 channel pointed to by the TCM[4:0] bits appear in the Transmit DS0 Monitor register (TDS0M) and
the DS0 channel pointed to by the RCM[4:0] bits appear in the Receive DS0 Monitor register (RDS0M). The
TCM[4:0] and RCM[4:0] bits should be programmed with the decimal decode of the appropriate T1 or E1 channel.
T1 channels 1 to 24 map to register values 0 to 23. E1 channels 1 to 32 map to register values 0 to 31. For
example, if DS0 channel 6 in the transmit direction and DS0 channel 15 in the receive direction needed to be
monitored, then the following values would be programmed into
TDS0SEL
REGISTER
register. In the receive direction, the RCM[4:0] bits in the
Table 8-29
shows the registers related to the control of transmit and receive DS0.
TCM4 = 0
TCM3 = 0
TCM2 = 1
TCM1 = 0
TCM0 = 1
ADDRESSES
FRAMER
63 of 276
1BBh
189h
012h
060h
RCM4 = 0
RCM3 = 1
RCM2 = 1
RCM1 = 1
RCM0 = 0
TDS0SEL
Transmit channel to be monitored.
Monitored data.
Receive channel to be monitored.
Monitored data.
and RDS0SEL:
RDS0SEL
DS26528 Octal T1/E1/J1 Transceiver
FUNCTION
register need to be properly