ADC08B3000RB/NOPB National Semiconductor, ADC08B3000RB/NOPB Datasheet
ADC08B3000RB/NOPB
Specifications of ADC08B3000RB/NOPB
Related parts for ADC08B3000RB/NOPB
ADC08B3000RB/NOPB Summary of contents
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... T +85°C) temperature range. A Ordering Information Industrial Temperature Range (-40°C < T ADC08B3000CIYB ADC08B3000RB © 2009 National Semiconductor Corporation ADC08B3000 Features ■ Single +1.9V ±0.1V Operation ■ Choice of SDR or DDR output clocking ■ Internal selectable 4K Data Buffer ■ Serial Interface for Extended Control ■ ...
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Block Diagram www.national.com 2 20160153 ...
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Pin Configuration Note: The exposed pad on the bottom of the package must be soldered to a ground plane to ensure rated performance. 3 20160102 www.national.com ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol 3 SCLK OutEdge / DDR / 4 SDATA 15 ADCCLK_RST CAL www.national.com Equivalent Circuit Serial Interface Clock (Input): LVCMOS - When the extended control mode is enabled, ...
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Pin Functions Pin No. Symbol Equivalent Circuit 14 FSR/ECE 127 CalDly / SCS 10 CLK+ 11 CLK − IN Description Full Scale Range Select / Extended Control Enable (Input): LVCMOS - In the Normal ...
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Pin Functions Pin No. Symbol 22 ADCCLK_RST+ 23 ADCCLK_RST CMO 126 CalRun 32 R EXT 34 Tdiode_P 35 Tdiode_N www.national.com Equivalent Circuit Sample Clock Reset (Input): LVDS - A positive differential pulse on these pins ...
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Pin Functions Pin No. Symbol Equivalent Circuit 72 D2<0> 71 D2<1> 70 D2<2> 69 D2<3> 68 D2<4> 67 D2<5> 66 D2<6> 65 D2<7> 75 DRDY2 89 D1<0> 90 D1<1> 91 D1<2> 92 D1<3> 93 D1<4> 94 D1<5> 95 D1<6> 96 ...
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Pin Functions Pin No. Symbol 45 REN 46 WEN 82 RCLK 81 RESET 79 WENSYNC 80 OR 115 FF 116 13, 16, 17, V 20, 25, A 28, 33, 128 www.national.com Equivalent Circuit Read Enable (Input): ...
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Pin Functions Pin No. Symbol Equivalent Circuit 40, 51, 62, 73 88, 99, 110, 121 12, GND 21, 24, 27 42, 53, 64, 74, DR GND 87, 97, 108, 119 29, 36, 37, 38, 39, ...
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... Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Analog Supply Voltage ( Voltage on Any Input Pin (Except Voltage (Maintaining Common Mode) Ground Difference |GND - DR GND| Input Current at Any Pin (Note 3) Package Input Current (Note 3) ≤ ...
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Symbol Parameter SNR Signal-to-Noise Ratio THD Total Harmonic Distortion 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion ANALOG INPUT AND REFERENCE CHARACTERISTICS Full Scale Analog Differential Input V IN Range V ...
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Symbol Parameter LVDS INPUT CHARACTERISTICS V Differential Clock Input Level ID I Input Current I C Input Capacitance (Note 10) IN LVCMOS INPUT CHARACTERISTICS V Logic High Input Voltage IH V Logic Low Input Voltage IL I Logic High Input ...
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Symbol Parameter AC ELECTRICAL CHARACTERISTICS - Sample Clock f Maximum Input Clock Frequency CLK1 f Minimum Input Clock Frequency CLK2 t Input Clock Duty Cycle CYC t Input Clock Low Time LC t Input Clock High Time HC t Sample ...
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Symbol Parameter AC ELECTRICAL CHARACTERISTICS - General Signals t Setup Time ADCCLK_RST± Hold Time ADCCLK_RST± Pulse Width ADCCLK_RST± PWR PD low to Rated Accuracy t WU Conversion (Wake-Up Time) t Calibration Cycle Time CAL t CAL ...
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Specification Definitions APERTURE (SAMPLING) DELAY is the amount of delay, measured from the sample edge of the Clock input, after which the signal present at the input pin is sampled inside the device. APERTURE JITTER ( the variation ...
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Transfer Characteristic www.national.com FIGURE 1. Input / Output Transfer Characteristic 16 20160122 ...
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Timing Diagrams FIGURE 4. Self Calibration and On-Command Calibration Timing FIGURE 2. Serial Interface Timing FIGURE 3. Clock Reset Timing 17 20160119 20160120 20160125 www.national.com ...
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FIGURE 6. Capture Buffer Write Enable Timing - 7 Input Clock Cycles www.national.com FIGURE 5. Capture Buffer Read Operation 18 20160160 20160161 ...
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FIGURE 7. Capture Buffer Write Enable Timing - 8 Input Clock Cycles FIGURE 8. Capture Buffer DRDY Timing - SDR/DDR 19 20160162 20160163 www.national.com ...
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FIGURE 9. Capture Buffer Beginning of READ Phase (OutEdge = 1b)(Note 14) FIGURE 10. Capture Buffer End of READ Phase (OutEdge = 1b)(Notes 14, 15) www.national.com 20 20160165 20160167 ...
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FIGURE 11. Capture Buffer Early REN Deassertion on READ Phase (OutEdge = 1b)(Note 14) 21 20160177 www.national.com ...
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FIGURE 12. Capture Buffer RESET on READ Phase (OutEdge = 1b)(Note 14) FIGURE 13. Capture Buffer Beginning of WRITE Phase www.national.com 22 20160169 20160171 ...
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FIGURE 14. Capture Buffer End of WRITE Phase (ASW = 1b)(Note 16) FIGURE 15. Capture Buffer End of WRITE Phase (ASW = 0b) Note 14: For (OutEdge = 0b), all activity occurs on falling edge of DRDY. Note 15: t ...
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Typical Performance Characteristics f =373 MHz, T =25°C unless otherwise stated DNL vs. TEMPERATURE DNL vs. CODE POWER CONSUMPTION vs. SAMPLE RATE www.national.com V =V =1.9V, f =1500 MHz (i.e., Sample Rate = 3 Gsps CLK ...
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ENOB vs. SUPPLY VOLTAGE 201601103 ENOB vs. INPUT FREQUENCY 201601105 SNR vs. SUPPLY VOLTAGE 201601107 ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE SNR vs. SAMPLE RATE 25 201601104 201601106 201601108 www.national.com ...
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SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY www.national.com THD vs. TEMPERATURE 201601109 THD vs. SAMPLE RATE 201601111 SFDR vs. TEMPERATURE 201601113 26 201601110 201601112 201601114 ...
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SFDR vs. SUPPLY VOLTAGE 201601115 SFDR vs. INPUT FREQUENCY 201601117 Spectral Response at FIN = 748 MHz 201601119 SFDR vs. SAMPLE RATE Spectral Response at FIN = 373 MHz Spectral Response at FIN = 1497 MHz 27 201601116 20160196 201601120 ...
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FULL POWER BANDWIDTH www.national.com 201601122 28 ...
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Functional Description The ADC08B3000 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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Control Modes Much of the user control can be accomplished with several control pins that are provided. Examples include initiation of the calibration cycle, power down mode and full scale range setting. However, the ADC08B3000 also provides an Extend- ...
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Feature SDR or DDR Clocking DDR Clock Phase SDR Data transitions with rising or falling DRDY edge Power-On Calibration Delay Full-Scale Range Input Offset Adjust Sample Clock Phase Adjustment Test Pattern Output The default state of the Extended Control Mode ...
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Programming the serial registers will also reduce dynamic performance of the ADC for the duration of the register access time. TABLE 3. Register Addresses 4-Bit Address Loading Sequence: A3 loaded after Fixed Header Pattern, A0 loaded last A3 ...
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Offset Adjust Addr: 2h (0010b) D15 D14 D13 D12 D11 D10 (MSB) Offset Value Sign Bits 15:8 Offset Value. The input offset of the ADC is adjusted linearly and ...
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Bit 14 BSIZE<0>: This bit in combination with BSIZE<1> (BIT 15) is used to select the buffer size of the Capture Buffer. The Capture Buffer is size adjustable and it cannot be split between the two LVCMOS data output ports. ...
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ADCs in a system. The ADCCLK_RST allows multiple ADCs in a system to be synchronized so that there is a known rela- tionship between the sampling times of all ADCs. The ADC08B3000 has been designed to accommodate systems which require ...
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Time Port D1 Port D2 OR T10 02h 01h T11 04h 03h T12 FDh FEh T13 FBh FCh T14 02h 01h T15 ... ... 1.7 CAPTURE BUFFER FUNCTIONAL DESCRIPTION With the integration of the Capture Buffer, the ADC08B3000 allows sampling ...
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RCLK alone to capture the data on the data output ports D1 and D2 is not practical. The Data Ready (DRDY) pins offer improved data capture capability by eliminating the impact of ...
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A.C. Coupled Input The easiest way to accomplish single-ended to differential conversion for a.c. signals is with an appropriate balun, as shown in Figure 18. This figure is a generic depiction of a single-ended to differential signal conversion using ...
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FIGURE 19. Example of Servoing the Analog Input with V CMO Be sure that the current drawn from the V exceed 100 μA. In Figure 19, R and R are used to adjust the differential ADJ- ADJ+ offset that can ...
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Hertz, at the ADC IN analog input. Note that the maximum jitter described above is the Root Sum Square, (RSS), of the jitter from all sources, including the in- ternal ADC clock ...
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On-Command Calibration To initiate an on-command calibration, bring the CAL pin high for a minimum of 80 input clock cycles after it has been low for a minimum of 80 input clock cycles. Holding the CAL pin high upon ...
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ADC supplies should be the same supply used for other ana- log circuitry, if not a dedicated supply. 2.6.1 Supply Voltage The ADC08B3000 is specified to operate with a supply volt- age of 1.9V ±0.1V very important to ...
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The thermal vias should be placed on a 1.2 mm grid spacing and have a diameter of 0.30 to 0.33 mm. These vias should be barrel plated to avoid solder wicking into the vias during the soldering process as this ...
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COMMON APPLICATION PITFALLS Failure to write all register locations when using extend- ed control mode. When using the serial interface, all six address locations must be written at least once with the de- fault or desired values before calibration ...
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Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP NS Package Number VNX128A 45 www.national.com ...
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