ADC08B3000RB/NOPB National Semiconductor, ADC08B3000RB/NOPB Datasheet - Page 44

• Manufacturer Part Number: ADC08B3000RB/NOPB
• Description: BOARD EVAL FOR ADC08B3000
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08B3000RB/NOPB

• Mfg Application Notes: ADC08zzzz Calibrating AppNote
• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended or 1 Differential
• Input Range: 810 mVpp
• Power (typ) @ Conditions: 1.2W @ 62MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08B3000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08B3000RB

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2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all six
address locations must be written at least once with the de-
fault or desired values before calibration and subsequent use
of the ADC.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
Care should be taken not to overdrive the inputs of the
ADC08B3000. Such practice may lead to conversion inaccu-
racies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in Section 1.1.4 The Analog
Inputs and Section 2.2 THE ANALOG INPUT, the Input com-
mon mode voltage must remain within 50 mV of the V
output, which has a variability with temperature that must also
be tracked. Distortion performance will be degraded if the in-
put common mode voltage is more than 50 mV from V
Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08B3000 as many high speed amplifiers will have
higher distortion than will the ADC08B3000, resulting in over-
all system performance degradation.
Driving the V
mentioned in Section 2.1 THE REFERENCE VOLTAGE, the
reference voltage is intended to be fixed to provide one of two
different full-scale values in the Normal Mode, or a range of
full-scale values in the Extended Control Mode. The reference
can not be changed by driving the V
driven.
BG
pin to change the reference voltage. As
BG
pin, which should not
CMO
CMO
.
44
Driving the clock input with an excessively high level
signal. As described in Section 2.3 THE SAMPLE CLOCK
INPUT, the ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change and a degradation of SFDR and SNR could re-
sult.
Inadequate input clock levels. As described in Section 2.3
THE SAMPLE CLOCK INPUT, insufficient input clock levels
can result in poor performance.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. Any of
these will cause the sampling interval to vary, causing exces-
sive output noise and a reduction in SNR performance.
Driving an LVCMOS input with LVPECL. The common
mode voltage of LVPECL is too high, so the ADC08B3000
may not properly interpret the input, so recognition of the in-
tended function may be marginal, intermittent, or non-exis-
tent.
Accessing the internal registers while a calibration is in
process. As indicated in Section 1.1.1 Calibration and Sec-
tion 1.3 THE SERIAL INTERFACE, the internal registers (via
the serial port) should not be accessed during calibration.
Doing so will impair the performance of the device until it is
re-calibrated correctly.
Failure to strictly observe ADCCLK_RST set-up and hold
times. The deassertion edge of the ADCCLK_RST pulse
must observe the specified setup and hold times (t
See Section 1.5 MULTIPLE ADC SYNCHRONIZATION. Al-
lowing for timing uncertainty in this timing is also important.
Failure to provide adequate heat removal. As described in
Section 2.6.2 Thermal Management, it is important to provide
adequate heat removal to ensure device reliability. This can
be done either with adequate air flow or the use of a simple
heat sink built into the board. The backside pad should be
grounded for best performance.
SR
, t
SH
).