ADC08B3000RB/NOPB National Semiconductor, ADC08B3000RB/NOPB Datasheet - Page 40

• Manufacturer Part Number: ADC08B3000RB/NOPB
• Description: BOARD EVAL FOR ADC08B3000
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08B3000RB/NOPB

• Mfg Application Notes: ADC08zzzz Calibrating AppNote
• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended or 1 Differential
• Input Range: 810 mVpp
• Power (typ) @ Conditions: 1.2W @ 62MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08B3000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08B3000RB

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and f
analog input.
Note that the maximum jitter described above is the Root Sum
Square, (RSS), of the jitter from all sources, including the in-
ternal ADC clock jitter, that added by the system to the ADC
input clock and input signals and that added by the ADC itself.
Since the effective jitter added by the ADC is beyond user
control, the best the user can do is to keep the sum of the
externally added input clock jitter and the jitter added by the
analog circuitry to the analog signal to a minimum.
2.3.1 Synchronizing Multiple ADCs (Manual Sample
Clock Phase Adjust)
To facilitate the synchronization of multiple ADC08B3000
chips to achieve net sample rates higher than that possible
with a single device, the ADC08B3000 has a manual clock
phase capability. This adjustment is only possible in the Ex-
tended Control Mode and is intended to allow the user to
accommodate subtle layout differences when between mul-
tiple ADCs. Register addresses Dh and Eh provide extended
mode access to fine and coarse adjustments. Use of Low
Frequency Sample Clock control, (register Eh; bit 10) is not
supported while using manual sample clock phase adjust-
ments.
It should be noted that by just enabling the phase adjust ca-
pability (register Eh; bit 15), degradation of dynamic perfor-
mance is expected, specifically SFDR. It is intended that very
small adjustments are used. That is just a few counts of the
fine adjustment and no adjustment of the coarse adjustment.
Larger increases in phase adjustments will begin to affect
SNR and ultimately ENOB. Therefore, the use of coarse
phase adjustment should be minimized in favor of better sys-
tem design.
It is best, then, to ensure that the proper phase relationships
exist between the analog input and clock signals presented
to each of the ADC08B3000s that are synchronized. That is,
use as much care in PCB design and layout that would be
used if there were no clock phase adjustment circuitry.
Figure 21 and Figure 22 indicate the typical phase adjustment
for the fine and coarse phase adjustments, respectively.
FIGURE 21. Typical Fine Clock Phase Adjust Range
IN
is the maximum input frequency, in Hertz, at the ADC
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2.4 CONTROL PINS
Without the use of the serial interface, six control pins provide
a range of possibilities in the operation of the ADC08B3000
to facilitate its use. These control pins provide Full-Scale Input
Range setting, Self Calibration, Calibration Delay, Output
Edge Synchronization choice, and Power Down.
2.4.1 Full-Scale Input Range Setting
The input full-scale range can be selected to be either of two
settings with the FSR control input (pin 14) in the Normal
Mode of operation. In the Extended Control Mode, the input
full-scale range may be set to any of 512 settings. See Section
1.4 REGISTER DESCRIPTION for more information.
2.4.2 Calibration
The ADC08B3000 calibration must be run to achieve speci-
fied performance. The calibration procedure is run upon pow-
er-up and can be run any time on command. The calibration
procedure is exactly the same whether there is an input clock
present upon power up or if the clock begins some time after
application of power. The calibration procedure is also exactly
the same whether it is a power-on calibration or an on-com-
mand calibration. The CalRun output is high while a calibra-
tion is in progress.
2.4.2.1 Power-On Calibration
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly. See Section 2.4.2.3 Calibration Delay.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08B3000 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2 On-Command Cal-
ibration.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 25 mW. The power consumption will
be normal after the clock starts.
FIGURE 22. Typical Coarse Clock Phase Adjust Range
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