ADC08B3000RB/NOPB National Semiconductor, ADC08B3000RB/NOPB Datasheet - Page 7

• Manufacturer Part Number: ADC08B3000RB/NOPB
• Description: BOARD EVAL FOR ADC08B3000
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC08B3000RB/NOPB

• Mfg Application Notes: ADC08zzzz Calibrating AppNote
• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 3G
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended or 1 Differential
• Input Range: 810 mVpp
• Power (typ) @ Conditions: 1.2W @ 62MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC08B3000
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: ADC08B3000RB

Pin Functions
Pin No.
72
71
70
69
68
67
66
65
75
89
90
91
92
93
94
95
96
86
Symbol
DRDY2
DRDY1
D2<0>
D2<1>
D2<2>
D2<3>
D2<4>
D2<5>
D2<6>
D2<7>
D1<0>
D1<1>
D1<2>
D1<3>
D1<4>
D1<5>
D1<6>
D1<7>
Equivalent Circuit
7
Digital Data Output 2
(Output): LVCMOS - When the REN input is
asserted and Two Port Enable, (TPE) is set to 1b in
the Capture Buffer register (addr: Fh, bit: 12), half of
the data is read from the capture buffer and
presented at this port synchronous with each rising
edge of Read CLK (RCLK). The data on this port is
the earlier sample data vs. the Digital Data Output 1
data. When Two Port Enable is set to 0b in the
Capture Buffer register, data output 2 is high-
impedance.
Data Ready 2
(Output): LVCMOS - DRDY is generated by RCLK
and is synchronized to the output data. The use of
this pin assists in eliminating the latency uncertainty
between when Read CLK (RCLK) transitions and
when data transitions at the output.
Digital Data Output 1
(Output): LVCMOS - When the REN input is
asserted, data is read from the capture buffer and
presented at this port synchronous with each rising
edge of Read CLK (RCLK). When the Two Port
Enable bit (TPE) is set to 1b in the Capture Buffer
register (addr: Fh, bit: 12), half of the data is
presented at this port. The data on this port is the
later sample data vs. the Digital Data Output 2 data.
When REN is deasserted, this output holds the data
from the previous read. When Two Port Enable is set
to 0b in the Capture Buffer register, this port presents
all of the data from the Capture Buffer.
Data Ready 1
(Output): LVCMOS - DRDY is generated by RCLK
and is synchronized to the output data. The use of
this pin assists in eliminating the latency uncertainty
between when Read CLK (RCLK) transitions and
when data transitions at the output.
Description
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