ADC08B3000RB/NOPB National Semiconductor, ADC08B3000RB/NOPB Datasheet - Page 14

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ADC08B3000RB/NOPB

Manufacturer Part Number
ADC08B3000RB/NOPB
Description
BOARD EVAL FOR ADC08B3000
Manufacturer
National Semiconductor
Series
PowerWise®r

Specifications of ADC08B3000RB/NOPB

Mfg Application Notes
ADC08zzzz Calibrating AppNote
Number Of Adc's
1
Number Of Bits
8
Sampling Rate (per Second)
3G
Data Interface
Serial
Inputs Per Adc
1 Single Ended or 1 Differential
Input Range
810 mVpp
Power (typ) @ Conditions
1.2W @ 62MSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC08B3000
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
ADC08B3000RB
www.national.com
AC ELECTRICAL CHARACTERISTICS - General Signals
t
t
t
t
t
t
t
t
SR
HR
PWR
WU
CAL
CAL_L
CAL_H
CalDly
Symbol
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power and ground pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
Note 7: To guarantee accuracy, it is required that V
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at T
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 1. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances include packaging capacitance values of 0.7 pF differential and 1 pF each input pin to ground, which are
isolated from the die capacitance by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Setup Time ADCCLK_RST±
Hold Time ADCCLK_RST±
Pulse Width ADCCLK_RST±
PD low to Rated Accuracy
Conversion (Wake-Up Time)
Calibration Cycle Time
CAL Pin Low Time
CAL Pin High Time
Calibration delay
CalDly = Low
Calibration delay
CalDly = High
Parameter
A
= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
A
and V
DR
be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
Differential ADCCLK_RST
Differential ADCCLK_RST
(Note 11)
See Figure 4
(Note 11)
See Figure 4
(Note 11)
See Section 1.1.1 Calibration, Figure 4,
and (Note 11)
See Section 1.1.1 Calibration, Figure 4,
and (Note 11)
Conditions
14
20160104
1.4 x 10
(Note 8)
Typical
A
), the current at that pin should be limited to
90
30
1
5
(Note 8)
Limits
2
2
80
80
4
25
31
CLK± Cyc.
CLK± Cyc.
CLK± Cyc.
CLK± Cyc.
CLK± Cyc.
CLK± Cyc.
(Limits)
Units
(max)
(max)
(min)
(min)
(min)
ps
ps
µs

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