ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 20

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

Due to errors in the inductance or DCR it may be necessary
to adjust the value of R
correctly. The effects of time constant mismatch can be seen
in the form of droop overshoot or undershoot during the
initial load transient spike, as shown in Figure 19. Follow the
steps below to ensure the R-C and inductor L/DCR time
constants are matched accurately.
After choosing a new value for R
necessary to adjust the value of R
load droop voltage. Use Equation 26 to obtain the new value
for R
Compensation
The two opposing goals of compensating the voltage
regulator are stability and speed. Depending on whether the
regulator employs the optional load-line regulation as
described in “Load Line (Droop) Regulation” on page 12,
there are two distinct methods for achieving these goals
1. Capture a transient event with the oscilloscope set to
2. Record ΔV
3. Select a new value, R
4. Replace R
about L/DCR/2 (sec/div). For example, with L = 1µH and
DCR = 1mΩ, set the oscilloscope to 500µs/div.
resistor based on the original value, R
Equation 27.
the error is corrected. Repeat the procedure if necessary.
R
S
ISL6310
COMP 2
.
FIGURE 18. DCR SENSING CONFIGURATION
PHASE1
PHASE2
,
DROOP
ICOMP
ISUM
IREF
=
COMP
1
and ΔV
R
COMP 1
with the new value and check to see that
COMP
,
2
C
V
as shown in Figure 19.
COMP,2
⋅
COMP
DROOP
Δ
----------
Δ
+
V
V
-
20
R
1
2
to match the time constants
S
COMP
, for the time constant
R
R
S
S
COMP
to obtain the desired full
I L2
I
L1
, it will most likely be
INDUCTOR
INDUCTOR
L
L
V
COMP,1
L
(s)
DCR
DCR
-
, using
(EQ. 27)
C
I
OUT
V
OUT
.
OUT
ISL6310
Compensating the Load Line Regulated Converter
The load-line regulated converter behaves in a similar
manner to a peak current mode controller because the two
poles at the output filter L-C resonant frequency split with the
introduction of current information into the control loop. The
final location of these poles is determined by the system
function, the gain of the current signal, and the value of the
compensation components, R
Since the system poles and zero are affected by the values
of the components that are meant to compensate them, the
solution to the system equation becomes fairly complicated.
Fortunately, there is a simple approximation that comes very
close to an optimal solution. Treating the system as though it
were a voltage-mode regulator, by compensating the L-C
poles and the ESR zero of the voltage mode approximation,
yields a solution that is always stable with very close to ideal
transient performance.
The feedback resistor, R
outlined in “Load Line (Droop) Regulation” on page 12
Select a target bandwidth for the compensated system, F
The target bandwidth must be large enough to assure
adequate transient performance, but smaller than 1/3 of the
FIGURE 20. COMPENSATION CONFIGURATION FOR
FIGURE 19. TIME CONSTANT MISMATCH BEHAVIOR
ΔV
1
R
1
LOAD-LINE REGULATED ISL6310 CIRCUIT
R
2
C
1
2
, has already been chosen as
C
(OPTIONAL)
1
2
and C
COMP
VDIFF
FB
1
ΔV
ΔI
2
ISL6310
August 7, 2008
V
I
TRAN
OUT
FN9209.4
0
.