ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 26

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
+5V
R
C
+12V
R
REF
REF
OFST
C
HF0
R
FS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
PGOOD
ENLL
VSEN
RGND
OVP
GND
IREF
2PH
VCC
FS
DAC
REF
REF1
VDIFF
OFST
REF0
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
OCSET
DROOP
R
R
OCSET
1
For information regarding Intersil Corporation and its products, see www.intersil.com
ICOMP
FB
26
FIGURE 27. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
C
R
C
1
ISL6310
COMP
COMP
C
R
2
ISUM
2
COMP
(MINIMIZE CONNECTION PATH)
PHASE1
UGATE2
PHASE2
UGATE1
LGATE1
LGATE2
BOOT1
BOOT2
C
LOCATE CLOSE TO IC
ISEN2
PVCC
ISEN1
SUM
to PVCC
R
C
C
R
S
BOOT1
S
BOOT2
R
ISL6310
R
ISEN2
ISEN1
C
HF01
C
C
HF2
HF1
+12V
+12V
C
BIN2
C
KEY
BIN1
LOCATE NEAR SWITCHING TRANSISTORS;
HEAVY TRACE ON CIRCUIT PLANE LAYER
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
(MINIMIZE CONNECTION PATH)
L
L
OUT1
OUT2
(MINIMIZE CONNECTION PATH)
C
LOCATE NEAR LOAD;
BOUT
(C
HFOUT
LOAD
August 7, 2008
)
FN9209.4